Patent US4811269A successfully refreshed from Google Patents.
US4811269A
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Bit slice multiplication circuit
Assignee: Hitachi Ltd
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Filing: 1986-10-08
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Granted: 1989-03-07
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Expires: 2006-10-08
Abstract
Abstract A bit slice multiplication circuit operating to slice a multiplier, produce products for the sliced multipliers and a multiplicand and sum the products to obtain the multiplication result. The circuit includes a slicing unit for slicing the multiplicand, multiplying units corresponding in number to the number of sliced multiplicands, and adding units provided in correspondence to the multiplying units and implementing summation for multiplication results from corresponding multiplying units while shifting the sliced portions of the multiplicand at each multiplying operation for sliced multipliers and multiplicands by the multiplying units, the multiplication result being obtained by summing all summation results produced by the adding units.
Inventors
- 👤 Kenji Hirose
- 👤 Tadaaki Bandoh
- 👤 Hidekazu Matsumoto
- 👤 Shinichiro Yamaguchi
- 👤 Hirokazu Hirayama
- 👤 Hiroaki Nakanishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3896
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
335 words
A multiplication circuit comprising: a first register for holding a multiplier having a length of 2m-by-n bits; first means for sequentially outputting n sets of 2m bits of the multiplier from said first register, one set at one time; decoder means for decoding a set of bits taken out by said first means; a second register for holding a multiplicand having a length 2m-by-n bits, said second register including shift means operating to shift the bit position of the multiplicand by 2m-bits in the ascending direction of bit position cyclically to produce a 2m-bit output for each multiplying operation by each ultiplier set; n multiplying units, each corresponding to one of the n sets of 2m-bit outputs from said shift means and each implementing multiplication for the 2m-bits of the multiplicand from said shift means and the output of said decoder means; n adding units, each corresponding to one of said n multiplying units, each adding unit incuding an adder and registers for holding a sum and carry produced by said addeer, each adding unit adapted for implementing summation for a high-order half bit portion of the output of the corresponding multiplying unit, a low-order half bit portion of the output of the cyclically next higher-order multiplying unit with respect to the corresponding multiplying unit and the contents of said register, with the result of the summation being held in said register, summation for the contents of said register and a low-order half bit portion of a product for a set of bits of the lowest-order portion of the multiplicand, among the multiplication results from multiplying units, and a sequentially taken out multiplier being carried out merely for producing a carry output, separately from summations for high-order half bit portions of the outputs of the cyclically next lower-order multiplying units; and summing means for summing respectively sums and carries held in the registers of said adding units produced as a result of summations for all multiplication results, and outputting the result of the multiplying operation.
Claim 2
Dependent Claim
335 words
A multiplication circuit comprising: a first register for holding a multiplier having a length of 2m-by-n bits; first means for sequentially outputting n sets of 2m bits of the multiplier from said first register, one set at one time; decoder means for decoding a set of bits taken out by said first means; a second register for holding a multiplicand having a length 2m-by-n bits, said second register including shift means operating to shift the bit position of the multiplicand by 2m-bits in the ascending direction of bit position cyclically to produce a 2m-bit output for each multiplying operation by each ultiplier set; n multiplying units, each corresponding to one of the n sets of 2m-bit outputs from said shift means and each implementing multiplication for the 2m-bits of the multiplicand from said shift means and the output of said decoder means; n adding units, each corresponding to one of said n multiplying units, each adding unit incuding an adder and registers for holding a sum and carry produced by said addeer, each adding unit adapted for implementing summation for a high-order half bit portion of the output of the corresponding multiplying unit, a low-order half bit portion of the output of the cyclically next higher-order multiplying unit with respect to the corresponding multiplying unit and the contents of said register, with the result of the summation being held in said register, summation for the contents of said register and a low-order half bit portion of a product for a set of bits of the lowest-order portion of the multiplicand, among the multiplication results from multiplying units, and a sequentially taken out multiplier being carried out merely for producing a carry output, separately from summations for high-order half bit portions of the outputs of the cyclically next lower-order multiplying units; and summing means for summing respectively sums and carries held in the registers of said adding units produced as a result of summations for all multiplication results, and outputting the result of the multiplying operation.
Claim 3
Dependent Claim
56 words
A multiplication circuit according to claim 1 further comprising register units for holding the outputs of said multiplying units, said adding units adapted for implementing the summing process by fetching the outputs of multiplying units held in said register units, said multiplying units implementing the next multiplying process while said adding units implement the summing process.
Claim 4
Dependent Claim
39 words
A multiplication circuit according to claim 1 wherein 2n of said multiplying units are provided, two multiplying units in each of n-sets of multiplying units operating identically, two multiplying units being connected to each of said adding units separately.
Claim 5
Dependent Claim
56 words
A multiplication circuit according to claim 3 further comprising register units for holding the outputs of said multiplying units, said adding units adapter for implementing the summing process by fetching the outputs of multiplying units held in said register units, said multiplying units implementing the next multiplying process while said adding units implement the summing process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |