Limited shift signal processing system and method

Claim 2

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; a plurality of summing means; providing means; means for generating at least one modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs to modify each preselected delay output by limited predetermined shifting of its place value, each of said means for shifting accomplishing one of a plurality of different place value shifts; said plurality of summing means, interposed between said delay means and said means for generating, for combining delay outputs preselected to undergo the same place value shift, each summing means producing a combined delay output value; said providing means, interposed between said summing means and said means for shifting, for providing each combined delay output value to at least one of said means for shifting; said steering means, interposed between said delay means and said plurality of summing means, for steering said preselected delay outputs to one or more of said summing means to effect a preselected distribution of said preselected delay outputs; and final summing means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 3

The limited-shift signal processor of claim 1 in which each said means for shifting accomplishes a single predetermined place value shift selected from zero to a limited maximum number of place value shifts.

Claim 4

The limited-shift signal processor of claim 1 in which there is only one means for shifting to accomplish each of said different predetermined place value shifts.

Claim 5

The limited-shift signal processor of claim 1 in which each of said means for shifting is operatively connected to one of said summing means.

Claim 6

The limited-shift signal processor of claim 1 further including means for selectively negating said preselected delay outputs.

Claim 7

The signal processor of claim 1 in which said means for steering includes means for selectively negating the preselected delay outputs.

Claim 8

The signal processor of claim 1 in which said means for generating generates at least two modified values from each delay output.

Claim 9

The limited-shift signal processor of claim 1 in which said means for steering includes means for selectively negating said preselected delay outputs.

Claim 10

The limited-shift signal processor of claim 1 in which said means for steering includes means for reconfiguring the steering of delay outputs.

Claim 11

The limited-shift signal processor of claim 9 in which said means for reconfiguring includes switching means for modifying the distribution of said preselected delay outputs to said means for shifting.

Claim 12

The limited-shift signal processor of claim 1 in which said means for generating further includes means for setting predesignated delay outputs to zero.

Claim 13

The limited-shift signal processor of claim 11 in which said means for steering directs each delay output to at least one of (a) one or more of said means for shifting and (b) said means for setting.

Claim 14

The limited-shift signal processor of claim 11 in which said means for steering directs each delay output to one of (a) said means for setting to zero, (b) said means for setting to zero and at least one of said means for shifting, (c) at least two different means for shifting, and (d) at least twice to the same means for shifting.

Claim 15

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; a plurality of summing means; providing means; means for generating at least one modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs, each said means for shifting accomplishing a predetermined place value shift selected from zero to a limited maximum number of place value shifts; said plurality of summing means, interposed between said delay means and said means for generating, for combining delay outputs preselected to undergo a same shift in place value, each summing means producing a combined delay output value; said providing means, interposed between said summing means and said means for shifting, for providing each combined delay output value to at least one of said means for shifting; said steering means, interposed between said delay means and said plurality of summing means, for steering said preselected delay outputs to one or more of said summing means to effect a preselected distribution of said preselected delay outputs; and final summing means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 16

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; a plurality of summing means; providing means; means for generating at least one modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs, each said means for shifting accomplishing a predetermined place value shift selected from zero to a limited maximum number of place value shifts; said plurality of summing means, interposed between said delay means and said means for generating, for combining delay outputs preselected to undergo a same shift in place value, each summing means producing a combined delay output value; said providing means, interposed between said summing means and said means for shifting, for providing each combined delay output value to at least one of said means for shifting; said steering means, interposed between said delay means and said plurality of summing means, for steering said preselected delay outputs to one or more of said summing means to effect a preselected distribution of said preselected delay outputs; and final summing means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 17

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; means for generating at least one modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs, each said means for shifting accomplishing a predetermined place value shift selected from zero to a limited maximum number of place value shifts; said means for generating further including means for setting pedesignated delay outputs to zero; means for steering each said preselected delay output to one or more of said means for shifting and for steering each said predesignated delay output to said means for setting; and xeans for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 18

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; means for generating at least one modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs, each said means for shifting accomplishing a predetermined place value shift selected from zero to a limited maximum number of place value shifts; said means for generating further including means for setting pedesignated delay outputs to zero; means for steering each said preselected delay output to one or more of said means for shifting and for steering each said predesignated delay output to said means for setting; and xeans for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 19

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; means for generating at least two modified values from substantially each delay output, at least one modified value being generated from each said delay output, including a plurality of means for shifting preselected delay outputs, corresponding to quantized weights having shift values, by digit positions commanded by the shift values to modify each preselected delay output by limited shifting of its place value, each shift value represented by a term having a limited number of nonzero digits; said means for generating further including means for setting to zero predesignated delay outputs corresponding to quantized weights representing a value of zero; said steering means, interposed between said delay means and said means for generating, for steering each said preselected delay output to one or more of said means for shifting and for steering each said predesignated delay output to said means for setting; means, connected to one or more of said means for shifting, for selectively negating said preselected delay outputs according to the polarity of said quantized weights; and final summing means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 20

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; means for generating at least two modified values from substantially each delay output, at least one modified value being generated from each said delay output, including a plurality of means for shifting preselected delay outputs, corresponding to quantized weights having shift values, by digit positions commanded by the shift values to modify each preselected delay output by limited shifting of its place value, each shift value represented by a term having a limited number of nonzero digits; said means for generating further including means for setting to zero predesignated delay outputs corresponding to quantized weights representing a value of zero; said steering means, interposed between said delay means and said means for generating, for steering each said preselected delay output to one or more of said means for shifting and for steering each said predesignated delay output to said means for setting; means, connected to one or more of said means for shifting, for selectively negating said preselected delay outputs according to the polarity of said quantized weights; and final summing means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal.

Claim 21

The limited-shift signal processor of claim 16 in which the term for each shift value has a single nonzero digit.

Claim 22

The limited-shift signal processor of claim 16 in which the quantized weights having a shift value and the quantized weights representing a value of zero are distributed together in at least two sets and the sets are adjusted to have the same number of quantized weights.

Claim 23

The limited-shift signal processor of claim 18 in which said delay means provides the same number of delay outputs as the number of quantized weights in each adjusted quantized weight set.

Claim 24

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: a plurality of signal processing units for operating on the input signal, each unit including: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; means for generating at least one weighted modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs to modify each preselected delay output by limited predetermined shifting of its place value; said steering means for steering said preselected delay outputs to one or more of said means for shifting; means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal; and final summer means for combining the weighted sum signals of said signal processing units to provide a final weighted sum signal of the input signal.

Claim 25

A high-speed, limited-shift signal processor for quantized weighting of an input signal, comprising: a plurality of signal processing units for operating on the input signal, each unit including: delay means for receiving the input signal and providing a plurality of delay outputs; steering means; means for generating at least one weighted modified value from each delay output, including a plurality of means for shifting the digit positions of preselected delay outputs to modify each preselected delay output by limited predetermined shifting of its place value; said steering means for steering said preselected delay outputs to one or more of said means for shifting; means for summing each of said place-value-shifted delay outputs generated by said means for shifting to obtain a weighted sum signal of the input signal; and final summer means for combining the weighted sum signals of said signal processing units to provide a final weighted sum signal of the input signal.

Claim 26

The limited-shift signal processor of claim 20 in which said signal processing units are connected to operate in parallel on the input signal.

Claim 29

The method of claim 22 further including negating selected ones of the delay outputs.

Claim 30

The method of claim 22 further including setting to zero the unselected delay outputs.

Claim 33

The method of claim 25 in which each quantized weight representing a nonzero weighting value is represented by a term having a single nonzero digit.

Claim 34

The method of claim 25 further including setting any unmatched delay outputs to zero.

Claim 35

The method of claim 25 further including negating selected ones of the matched delay outputs according to the polarity of the quantized weights.

Claim 36

The method of claim 25 further including: retaining residual error values generated during the conversion of the plurality of original weights into the first group of quantized weights; converting the residual error values into a second group of quantized weights such that each quantized weight is represented by a term having a limited number of nonzero digits; and providing a final weighted sum signal which is a function of the first and second group of quantized weights and the input signal.

Claim 37

The method of claim 29 in which the providing includes: receiving the input signal and delaying it to provide a plurality of second delay outputs; matching, to one of the second delay outputs, each quantized weight of the second group representing a nonzero weighting value; shifting the place value of each matched second delay output to modify it by the limited number of nonzero digits of that quantized weight of the second group; summing each of the place-value-shifted delay outputs to obtain a second weighted sum signal of the input signal; and combining the first and second weighted sum signals to provide the final weighted sum signal of the input signal.