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US4811082A Expired / Lapsed US ⏱️ 0.0 years remaining

High performance integrated circuit packaging structure

Assignee: International Business Machines Corp
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Filing: 1986-11-12
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Granted: 1989-03-07
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Expires: 2006-11-12
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Abstract

Abstract A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

Inventors

  • 👤 Scott L. Jacobs
  • 👤 Perwaiz Nihal
  • 👤 Burhan Ozmat
  • 👤 Henri D. Schnurmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:47
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W90/00; H10W90/701; H10W90/721; H10W90/724

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 155 words
A high performance integrated circuit packaging structure comprising: a substrate; alternating insulation and conductive layers on said substrate; a plurality of internal circuits integrated into discrete semiconductor segments; said discrete semiconductor segments mounted on an uppermost conductive layer; said semiconductor segments placed in close enough proximity to each other so that performance is equal to that of a monolithic integrated circuit structure; an array of feedthroughs in said substrate, a plurality of said feedthroughs located beneath said semiconductor segments; wiring means incorporated into at least two of said conductive layers for providing connections for said internal circuits; said wiring means being adapted for maintaining a noise voltage level in said integrated circuit structure which is substantially less than the lowest logic threshold voltage in said integrated circuit structure so that said plurality of internal circuit groups collectively have a number of drivers and receivers which is less than the number provided for by Rent's Rule.
Claim 2
Dependent Claim 155 words
A high performance integrated circuit packaging structure comprising: a substrate; alternating insulation and conductive layers on said substrate; a plurality of internal circuits integrated into discrete semiconductor segments; said discrete semiconductor segments mounted on an uppermost conductive layer; said semiconductor segments placed in close enough proximity to each other so that performance is equal to that of a monolithic integrated circuit structure; an array of feedthroughs in said substrate, a plurality of said feedthroughs located beneath said semiconductor segments; wiring means incorporated into at least two of said conductive layers for providing connections for said internal circuits; said wiring means being adapted for maintaining a noise voltage level in said integrated circuit structure which is substantially less than the lowest logic threshold voltage in said integrated circuit structure so that said plurality of internal circuit groups collectively have a number of drivers and receivers which is less than the number provided for by Rent's Rule.
Claim 3
Dependent Claim 87 words
The packaging structure of claim 1 wherein said wiring means are comprised of at least two layers, each layer having substantially coplanar power and signal lines, wherein substantially all of said substantially coplanar signal lines are separated from each other by at least one substantially coplanar power line, and said power lines of each layer are electrically interconnected so that the voltage levels of any two interconnected power lines are the same, whereby at least one power plane at a particular voltage level exists in three dimensions.
Claim 4
Dependent Claim 15 words
The packaging structure of claim 1 wherein said substrate is made of a semiconductor material.
Claim 5
Dependent Claim 23 words
The integrated circuit packaging structure of claim 1 wherein said wiring means comprise a plurality of signal wiring lines and power distribution structures.
Claim 6
Dependent Claim 83 words
The integrated circuit packaging structure of claim 1 wherein said plurality of internal circuit groups collectively has a number of drivers and receivers which is less than the number provided for by Rent's Rule, and greater than or equal to the following expression: ##EQU4## wherein n is equal to said plurality of internal circuit groups; S=the number of drivers and receivers required according to Rent's Rule; Cm is equal to the number of logic circuits in each internal circuit group, and R=Rent's exponent.
Claim 7
Dependent Claim 83 words
The integrated circuit packaging structure of claim 2 wherein said plurality of internal circuit groups collectively has a number of drivers and receivers which is less than the number provided for by Rent's Rule, and greater than or equal to the following expression: ##EQU5## wherein n is equal to said plurality of internal circuit groups; S=the number of drivers and receivers required according to Rent's Rule; Cm is equal to the number of logic circuits in each internal circuit group, and R=Rent's exponent.
Claim 8
Dependent Claim 36 words
The integrated circuit packaging structure of claim 1 wherein said wiring means provide a ratio of lowest signal threshold voltage to coupled noise plus delta-I noise of greater than or equal to approximately 10 to 1.
Claim 9
Dependent Claim 36 words
The integrated circuit packaging structure of claim 2 wherein said wiring means provide a ratio of lowest signal threshold voltage to coupled noise plus delta-I noise of greater than or equal to approximately 10 to 1.
Claim 10
Dependent Claim 13 words
The packaging structure of claim 3 wherein said substrate is made of silicon.
Claim 11
Dependent Claim 28 words
The packaging structure of claim 1 wherein said semiconductor segments are mounted to said uppermost conductive layer by solder balls between approximately 1 and 3 mils in diameter.
Claim 12
Dependent Claim 37 words
The packaging structure of claim 9 wherein there are signal feedthroughs through said silicon, said signal feedthroughs comprising; a central conductor, a low expansion dielectric substantially surrounding said conductor, and an insulator surrounding said low expansion dielectric.
Claim 13
Dependent Claim 13 words
The packaging structure of claim 11 wherein said low expansion dielectric is polyimide.
Claim 14
Dependent Claim 18 words
The packaging structure of claim 1 wherein said array of feedthroughs is comprised of substantially all power feedthroughs.
Claim 15
Dependent Claim 19 words
The packaging structure of claim 1 wherein said array of feedthroughs is comprised of both signal and power feedthroughs.
Claim 16
Dependent Claim 27 words
The packaging structure of claim 2 wherein said signal wiring lines are between approximately 3 and 10 microns wide, and between approximately 3 and 10 microns tall.
Claim 17
Dependent Claim 21 words
The packaging structure of claim 15 wherein said signal and power lines are spaced between approximately 5 and 10 microns apart.
Claim 18
Dependent Claim 32 words
The integrated circuit packaging structure of claim 1 further comprising at least one other of said integrating circuit packaging structures, said structures being connected to each other and to a mother substrate.
Claim 19
Dependent Claim 15 words
The packaging structure of claim 17 wherein said mother substrate is a multi-layered ceramic substrate.
Claim 20
Dependent Claim 19 words
The packaging structure of claim 17 wherein said connections between said integrated circuit packaging structures are made by decals.
Claim 21
Dependent Claim 26 words
The packaging structure of claim 19 wherein said decals comprise a flexible carrier layer having at least one signal wiring layer and one ground layer therein.
Claim 22
Dependent Claim 19 words
The packaging structure of claim 3 wherein at least one of said drivers is present in said semiconductor substrate.
Claim 23
Dependent Claim 15 words
The packaging structure of claim 17 wherein said substrate is made of a semiconductor material.
Claim 24
Dependent Claim 19 words
The packaging structure of claim 22 wherein at least one of said drivers is present in said semiconductor substrate.
Claim 25
Dependent Claim 26 words
The packaging structure of claim 3 wherein there are substantially no drivers in said discrete semiconductor segments, and a plurality of drivers in said semiconductor substrate.
Claim 26
Dependent Claim 26 words
The packaging structure of claim 22 wherein there are substantially no drivers in said discrete semiconductor segments, and a plurality of drivers in said semiconductor substrate.

References Cited (Backward Citations)

US4667220A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-03-06 1992-09-05 1993-03-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-03-06 1996-09-05 1997-03-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-03-06 2000-09-05 2001-03-07 $7700.00 Window Closed / Lapsed

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