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Patent US4811064A successfully refreshed from Google Patents.
US4811064A
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Static induction transistor and integrated circuit device using same
Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
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Filing: 1987-01-28
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Granted: 1989-03-07
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Expires: 2007-01-28
Abstract
Abstract A static induction transistor (SIT) which is made to operate with a forward gate bias by maintaining the width of the channel region at an appropriate value. Such an improved SIT is used as the inverter transistor in a merged transistor logic (MTL) semiconductor IC (integrated circuit) to reduce the time delay-power product by an order or more. The collector region of a bipolar load transistor is continuous to or also serves as the gate region of the inverter SIT. A plurality of channel regions are formed penetrating through this collection/gate region. This SIT is simple in structure, which enables a marked increase in the integration density.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Bogdan M. Wilamowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/091; H10; H10D; H10D10/00; H10D10/40; H10D10/461; H10D10/60; H10D12/00; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/134; H10D62/17; H10D62/343; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406; H10D84/409; H10D89/00; H10D89/211; H10D89/213; H10D89/217
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
328 words
A semiconductor integrated circuit comprising a merged transistor logic device including at least one driver transistor, and at least one load transistor, said device comprising: a semiconductor wafer having a first and a second principal surface; a first semiconductor region of a first conductivity type and a low impurity concentration and formed in the first principal surface of said semiconductor wafer, said first semiconductor region carrying a channel region of said inverter transistor and forming a base region of said load transistor; at least one heavily doped second semiconductor region of a second conductivity type opposite to said first conductivity type and formed in said first semiconductor region and at least partially exposed to said first principal surface, the second heavily doped region forming a collector region of said load transistor and a gate region for said driver transistor; at least one heavily doped third semiconductor region of the second conductivity type forming an emitter region for said load transistor; at least one channel region of said first conductivity type associated with said at least one driver transistor and having a low impurity concentration, said channel region being formed through said heavily doped second semiconductor region into said first semiconductor region thereby to serve as a channel of said driver transistor, said channel region being formed so as to have a width of about one-third to two-thirds of the width of a depletion layer spread established by the built-in potential due to the second semiconductor region; at least one heavily doped drain region of said first conductivity type associated with said at least one driver transistor, and being formed in said first principal surface of the semiconductor wafer and located adjacent to said channel region; and a heavily doped source region of said first conductivity type associated with said at least one driver transistor being formed in said semiconductor wafer adjacent to said channel region below said drain region, the source region being larger than said drain region.
Claim 2
Dependent Claim
328 words
A semiconductor integrated circuit comprising a merged transistor logic device including at least one driver transistor, and at least one load transistor, said device comprising: a semiconductor wafer having a first and a second principal surface; a first semiconductor region of a first conductivity type and a low impurity concentration and formed in the first principal surface of said semiconductor wafer, said first semiconductor region carrying a channel region of said inverter transistor and forming a base region of said load transistor; at least one heavily doped second semiconductor region of a second conductivity type opposite to said first conductivity type and formed in said first semiconductor region and at least partially exposed to said first principal surface, the second heavily doped region forming a collector region of said load transistor and a gate region for said driver transistor; at least one heavily doped third semiconductor region of the second conductivity type forming an emitter region for said load transistor; at least one channel region of said first conductivity type associated with said at least one driver transistor and having a low impurity concentration, said channel region being formed through said heavily doped second semiconductor region into said first semiconductor region thereby to serve as a channel of said driver transistor, said channel region being formed so as to have a width of about one-third to two-thirds of the width of a depletion layer spread established by the built-in potential due to the second semiconductor region; at least one heavily doped drain region of said first conductivity type associated with said at least one driver transistor, and being formed in said first principal surface of the semiconductor wafer and located adjacent to said channel region; and a heavily doped source region of said first conductivity type associated with said at least one driver transistor being formed in said semiconductor wafer adjacent to said channel region below said drain region, the source region being larger than said drain region.
Claim 3
Dependent Claim
49 words
A semiconductor integrated circuit according to claim 1, wherein said drive further comprises: said third semiconductor region being formed in the first semiconductor region and being partially exposed at the first principal surface, said third semiconductor region being separated from said second semiconductor region by said first semiconductor region.
Claim 4
Dependent Claim
112 words
A semiconductor integrated circuit according to claim 1 or 2, wherein said device further comprises: an embedded heavily doped fourth region of said second conductivity type formed in said first semiconductor region and adjacent to said source region of said at least on driver transistor but separated from said second semiconductor region of said second conductivity type, thereby forming barrier regions for defining the effective current path of said at least one driver transistor; and said heavily doped source region of said first conductivity type being partially exposed to said first semiconductor region, partially exposed to said embedded heavily doped fourth region, and at least partially exposed to said second principal surface.
Claim 5
Dependent Claim
51 words
A semiconductor integrated circuit according to claim 1 or 2, wherein said device comprises: said at least one heavily doped second semiconductor region has extensions into said channel region of said at least one driver transistor so that said channel region has a smaller cross-sectional area near said first semiconductor region.
Claim 6
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 1, wherein said device further comprises: said third semiconductor region of said second conductivity type formed adjacent to said first semiconductor region below said at least one heavily doped second semiconductor region.
Claim 7
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 5, wherein said heavily doped source region of said at least one driver transistor intervenes between said first semiconductor region and said third semiconductor region, said source region having windows at least below said second conductivity region.
References Cited (Backward Citations)
US4259681A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |