Arithmetic and logic operating unit

Claim 1

An arithmetic and logic unit for performing arithmetic and logic operations on externally supplied first digital input signal A and second digital input signal B in response to arithmetic mode indicating signals, and outputting a result thereof, said arithmetic and logic unit comprising: control means (14) for generating first (S 0 -S 5 ), second (C in , S 6 ) and third (C c ) internal control signals in response to said arithmetic mode indicating signals; selector means (10a-10d) for generating an absolute value of said first input signal A and a complement B of said second input signal B from said input signals A and B in response to said first internal control signals (S 0 -S 5 ) from said control means (14); adder means (6a-6d) for adding said absolute value |A| and said complement B/ from said arithmetic means (10a-10d) in response to said second internal control signals (C in , S 6 ) from said control means (14); first extraction means (2, 20a-20c, 21) for extracting a most significant bit of output from said adder means (6a-6d) in response to said third internal control signals (C c ) from said control means (14); second extraction means (3d) for extracting a most significant bit of said first input signal A; and output means (2, 20d, 21) for outputting a result signal responsive to a result of a three-level decision corresponding to a>B, |A|≦B and A<-B (where B>0), said result signal including an output of said first extraction means (2, 20a-20c, 21) and an output from said second extraction means (3d).