US4809306A
Expired / Lapsed
US
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RF modem with improved clock recovery circuit
Assignee: TE Connectivity Corp
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Filing: 1986-11-17
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Granted: 1989-02-28
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Expires: 2006-11-17
Abstract
Abstract In recovering clock information from received data, the voltage input to a voltage controlled oscillator (Q1) forming part of a phase locked loop (Q1, U3A, U2A, U3B, R10, C12, U4) is determined by comparing a voltage signal to a voltage reference that is precisely the midpoint of the voltage swing between a logic 0 and a logic 1 in the circuit. The voltage reference is generated using an exclusive OR gate (U3B) having one input tied to either the circuit voltage representing a logic 0 or the circuit voltage representing a logic 1. The second input to the exclusive OR gate (U3B) switches between a logic 1 and a logic 0 periodically such that the output of the exclusive OR gate (U3B) switches between the voltage level of a logic 1 and the voltage level of a logic 0 with a 50 percent duty cycle. An exclusive OR gate (U3C) is also used as a phase detector (U3 C) to detect the phase difference between a clock signal derived from the phase locked loop oscillator output and the received data. The phase detector (U3C) output is compared (U4) to the reference voltage; any difference therebetween adjusts the input voltage to the voltage controlled oscillator and therefore the output frequency of the oscillator (Q1) to maintain a phase difference between the clock signal (CLK) derived from the oscillator (Q1) output and the clock signal in the incoming data to permit sampling the incoming data at a 90 degree phase shift. The voltage reference (U3B) and phase detector (U3C) exclusive OR gates are fabricated on the same wafer and have the same resistive load (R10, R12). In this manner, the voltage reference generated by the exclusive OR gate remains precisely at the midpoint of the voltage swing between logic level 0 and logic level 1, inherently compensating for changes in temperature and other effects.
Inventors
- 👤 Gerald L. Somer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:52
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
188 words
Apparatus for recovering timing information from a data stream, comprising digital circuit means for establishing a reference voltage signal at precisely the midpoint of the voltage levels representing a logic 0 and a logic 1; phase detector means for detecting the phase difference between a clock signal and the data stream, said phase detector means having a first input port for receiving the clock signal, a second input port for receiving the data stream and an output port at which the detected phase difference is presented; amplifier means for receiving the voltage reference signal and for receiving the detected phase difference and for amplifying the difference therebetween, said amplifier means having a first input port for receiving the voltage reference signal, a second input port for receiving the detected phase difference, and an output port at which the amplified difference signal is presented; and voltage controlled oscillator means for receiving the amplified difference signal, said voltage controlled oscillator producing an output signal having a frequency that varies with the amplified difference signal, said output signal providing the input to the first input port of said phase detector means.
Claim 2
Dependent Claim
188 words
Apparatus for recovering timing information from a data stream, comprising digital circuit means for establishing a reference voltage signal at precisely the midpoint of the voltage levels representing a logic 0 and a logic 1; phase detector means for detecting the phase difference between a clock signal and the data stream, said phase detector means having a first input port for receiving the clock signal, a second input port for receiving the data stream and an output port at which the detected phase difference is presented; amplifier means for receiving the voltage reference signal and for receiving the detected phase difference and for amplifying the difference therebetween, said amplifier means having a first input port for receiving the voltage reference signal, a second input port for receiving the detected phase difference, and an output port at which the amplified difference signal is presented; and voltage controlled oscillator means for receiving the amplified difference signal, said voltage controlled oscillator producing an output signal having a frequency that varies with the amplified difference signal, said output signal providing the input to the first input port of said phase detector means.
Claim 3
Dependent Claim
28 words
Apparatus for recovering timing information from a data stream as recited in claim 1, further comprising: means for convertin the oscillator output signal to a square wave signal.
Claim 4
Dependent Claim
32 words
Apparatus for recovering timing information from a data stream as recited in claim 2, wherein the reference voltage signal establishing means further comprises an input port for receiving the square wave signal.
Claim 5
Dependent Claim
50 words
Apparatus for recovering timing information from a data stream as recited in claim 1, wherein the reference voltage establishing means comprises a logic gate, the output of which produces a 50 percent duty cycle signal oscillating between the voltage representing a logic 0 and the voltage representing a logic 1.
Claim 6
Dependent Claim
23 words
Apparatus for recovering timing information from a data stream as recited in claim 4, wherein the logic gate is an exclusive OR gate.
Claim 7
Dependent Claim
31 words
Apparatus for recovering timing information from a data stream as recited in claim 4, wherein one input to the logic gate is tied to the voltage level representing a logic 0.
Claim 8
Dependent Claim
31 words
Apparatus for recovering timing information from a data stream as recited in claim 4, wherein one input to the logic gate is tied to the voltage level representing a logic 1.
Claim 9
Dependent Claim
50 words
Apparatus for recovering timing information from a data stream as recited in claim 4, wherein one input to the logic gate switches between the voltage level representing a logic 0 and the voltage level representing a logic 1 at a rate that is a multiple of the oscillator output frequency.
Claim 10
Dependent Claim
25 words
Apparatus for recovering timing information from a data stream as recited in claim 4, wherein the phase detector means is comprised of a logic gate.
Claim 11
Dependent Claim
33 words
Apparatus for recovering timing information from a data stream as recited in claim 9, further comprising an identical resistive load on the phase detector logic gate and the reference voltage establishing logic gate.
Claim 12
Dependent Claim
32 words
Apparatus for recovering timing information from a data stream as recited in claim 9, wherein the phase detector logic gate and the reference voltage establishing logic gate are on the same chip.
Claim 13
Dependent Claim
33 words
Apparatus for recovering timing information from a data stream as recited in claim 11, further comprising an identical resistive load on the phase detector logic gate and the reference voltage establishing logic gate.
Claim 14
Dependent Claim
220 words
A modem having a clock recovery circuit for recovering timing information from a data stream, comprising: receiving means for receiving and decoding a radio frequency signal into a data stream; and a clock recovery circuit for recovering timing information from the data stream, comprising digital circuit means for establishing a reference voltage at precisely the midpoint of the voltage levels representing a logic 0 and a logic 1; phase detector means for detecting the phase difference between a clock signal and a data stream, said phase detector means having a first input port for receiving the clock signal, a second input port for receiving the data stream and an output port at which the detected phase difference is presented; amplifier means for receiving the voltage reference and for receiving the detected phase difference and for amplifying the difference therebetween, said amplifier means having a first input port for receiving the voltage reference signal, a second input port for receiving the detected phase difference, and an output port at which the amplifier difference signal is presented; and voltage controlled oscillator means for receiving the amplified difference signal, said voltage controlled oscillator producing an outut signal having a frequency that varies with the amplified difference signal, said output signal providing the input to the first input port of said phase detector means.
Claim 15
Dependent Claim
220 words
A modem having a clock recovery circuit for recovering timing information from a data stream, comprising: receiving means for receiving and decoding a radio frequency signal into a data stream; and a clock recovery circuit for recovering timing information from the data stream, comprising digital circuit means for establishing a reference voltage at precisely the midpoint of the voltage levels representing a logic 0 and a logic 1; phase detector means for detecting the phase difference between a clock signal and a data stream, said phase detector means having a first input port for receiving the clock signal, a second input port for receiving the data stream and an output port at which the detected phase difference is presented; amplifier means for receiving the voltage reference and for receiving the detected phase difference and for amplifying the difference therebetween, said amplifier means having a first input port for receiving the voltage reference signal, a second input port for receiving the detected phase difference, and an output port at which the amplifier difference signal is presented; and voltage controlled oscillator means for receiving the amplified difference signal, said voltage controlled oscillator producing an outut signal having a frequency that varies with the amplified difference signal, said output signal providing the input to the first input port of said phase detector means.
Claim 16
Dependent Claim
43 words
A modem as recited in claim 13, wherein the reference voltage establishing means comprises a logic gate, the output of which produces a 50 percent duty cycle signal oscillating between the voltage representing a logic 0 and the voltage representing a logic 1.
Claim 17
Dependent Claim
16 words
A modem as recited in claim 14, wherein the logic gate is an exclusive OR gate.
Claim 18
Dependent Claim
24 words
A modem as recited in claim 14, wherein one input to the logic gate is tied to the voltage level representing a logic 0.
Claim 19
Dependent Claim
24 words
A modem as recited in claim 14, wherein one input to the logic gate is tied to the voltage level representing a logic 1.
Claim 20
Dependent Claim
18 words
A modem as recited in claim 14, wherein the phase detector means is comprised of a logic gate.
Claim 21
Dependent Claim
26 words
A modem as recited in claim 18, further comprising an identical resistive load on the phase detector logic gate and the reference voltage establishing logic gate.
Claim 22
Dependent Claim
25 words
A modem as recited in claim 18, wherein the phase detector logic gate and the reference voltage establishing logic gate are on the same chip.
Claim 23
Dependent Claim
26 words
A modem as recited in claim 20 further comprising an identical resistive load on the phase detector logic gate and the reference voltage establishing logic gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |