§
Luxuse
Patent Intelligence
Sign In
Patent US4809227A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4809227A Expired / Lapsed US ⏱️ 0.0 years remaining

Read only memory device having memory cells each storing one of three states

Assignee: Fujitsu Ltd
•
Filing: 1987-08-05
•
Granted: 1989-02-28
•
Expires: 2007-08-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A read only memory device including: a memory cell array having a plurality of memory cells each storing one of three states; selection means, connected to the memory cell array, for selecting a pair of the memory cells from the memory cell array simultaneously in accordance with an address signal; a first sense amplifier, operatively connected to one of the pair of the memory cells, for producing a three bit output corresponding to the state stored in the one of the pair of the memory cells selected by the selection means; and a second sense amplifier, operatively connected another of the pair of memory cells, for producing a three bit output corresponding to the state stored in the another of the pair of the memory cells selected by the selection means. The device further includes decoder means, connected to the first and second sense amplifiers, for receiving the three bit outputs of the first and second amplifiers and producing a binary three bit output corresponding to the states stored in the pair of memory cells.

Inventors

  • 👤 Yasuo Suzuki
  • 👤 Yasuaki Suzuki
  • 👤 Nobuo Ikuta

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 17:52
CPC Classifications
G; G06; G06F; G06F12/00; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C17/00; G11C7/00; G11C7/10; G11C7/1006

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 205 words
A read only memory device comprising: a memory cell array having a plurality of memory cells each storing one of three states; a selection means, connected to said memory cell array, for selecting two memory cells simultaneously from said memory cell array in accordance with an address signal; a first sense amplifier, connected to one of the two selected memory cells , for producing a three bit output corresponding to the state stored in the one of the two selected memory cells selected by said selection means; a second sense amplifier, connected to another of the two selected memory cells, for producing a three bit output corresponding to the state stored in said another of the two selected memory cells selected by said selection means; and a decoder means, connected to said first and second sense amplifiers, for receiving the three bit outputs of said first and second amplifiers and for producing a three bit binary data output corresponding to the states stored in the two selected memory cells, said decoder means comprising a read only memory receiving said three bit output from said first sense amplifier as a column address and said three bit output from said second sense amplifier as a row address.
Claim 2
Dependent Claim 205 words
A read only memory device comprising: a memory cell array having a plurality of memory cells each storing one of three states; a selection means, connected to said memory cell array, for selecting two memory cells simultaneously from said memory cell array in accordance with an address signal; a first sense amplifier, connected to one of the two selected memory cells , for producing a three bit output corresponding to the state stored in the one of the two selected memory cells selected by said selection means; a second sense amplifier, connected to another of the two selected memory cells, for producing a three bit output corresponding to the state stored in said another of the two selected memory cells selected by said selection means; and a decoder means, connected to said first and second sense amplifiers, for receiving the three bit outputs of said first and second amplifiers and for producing a three bit binary data output corresponding to the states stored in the two selected memory cells, said decoder means comprising a read only memory receiving said three bit output from said first sense amplifier as a column address and said three bit output from said second sense amplifier as a row address.
Claim 3
Dependent Claim 19 words
A read only memory device according to claim 1, wherein the read only memory comprises a matrix of transistors.
Claim 4
Dependent Claim 29 words
A read only memory device according to claim 1, wherein said memory cells are comprised of transistors each having a mutual conductance corresponding to one of the three states.
Claim 5
Dependent Claim 28 words
A device according to claim 3, wherein the adjustment of mutual conductance gm can be carried out by variation of a dopant of impurities in each cell transistor.
Claim 6
Dependent Claim 24 words
A device according to claim 3, wherein the adjustment of mutual conductance gm can be carried out by variation of the effective gate width.

References Cited (Backward Citations)

US4327424A Cited
US4653023A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-28 1992-08-29 1993-02-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-28 1996-08-29 1997-02-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-28 2000-08-29 2001-02-28 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag