US4807009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Lateral transistor
Assignee: Canon Inc
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Filing: 1988-07-13
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Granted: 1989-02-21
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Expires: 2008-07-13
Abstract
Abstract In a lateral transistor having a first semiconductor region of one conductivity type, and an emitter region and a collector region both having the opposite conductivity type and disposed in the first semiconductor region; a second semiconductor region having the opposite conductivity type is disposed opposite to the emitter region with respect to the collector region. The thus obtained lateral transistor has a characteristic that a current flowing to the substrate is prevented under a saturation operation state and is suitably used to form, e.g., a current-mirror type constant-current circuit constituting a switching device having improved threshold characteristics.
Inventors
- 👤 Ikuo Fushimi
- 👤 Takamasa Sakuragi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:14
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/60; H10D62/00; H10D62/10; H10D62/113; H10D62/114
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
251 words
A switching device, comprising: (1) a first transistor of the PNP structure comprising: a base region, an emitter region, a first collector region and a second collector region each having the same conductivity type as that of the emitter region, and a semiconductor region (A) disposed outside the first and second collector regions with respect to the emitter region and having the same conductivity type as that of the collector regions; (2) a second transistor of the NPN structure, the collector of the second transistor being connected to the base and the first collector of the first transistor; (3) a third transistor of the NPN structure having an emitter area 1/n times that of the second transistor, the collector of the third transistor being connected to the second collector of the first transistor; (4) a fourth transistor of the PNP structure, the base of the fourth transistor being connected to the second collector of the first transistor and the collector of the third transistor; load circuit means being connected to the collector of the fourth transistor; a power supply terminal being connected respectively to the emitter of the first transistor, to the bases of the second and third transistors respectively through a first resistor of a high resistance, and to the emitter of the fourth transistor; an input current terminal being connected respectively to the semiconductor region (A) of the first transistor, to the emitter of the second transistor through a second resistor, and to the emitter of the third transistor.
Claim 2
Dependent Claim
251 words
A switching device, comprising: (1) a first transistor of the PNP structure comprising: a base region, an emitter region, a first collector region and a second collector region each having the same conductivity type as that of the emitter region, and a semiconductor region (A) disposed outside the first and second collector regions with respect to the emitter region and having the same conductivity type as that of the collector regions; (2) a second transistor of the NPN structure, the collector of the second transistor being connected to the base and the first collector of the first transistor; (3) a third transistor of the NPN structure having an emitter area 1/n times that of the second transistor, the collector of the third transistor being connected to the second collector of the first transistor; (4) a fourth transistor of the PNP structure, the base of the fourth transistor being connected to the second collector of the first transistor and the collector of the third transistor; load circuit means being connected to the collector of the fourth transistor; a power supply terminal being connected respectively to the emitter of the first transistor, to the bases of the second and third transistors respectively through a first resistor of a high resistance, and to the emitter of the fourth transistor; an input current terminal being connected respectively to the semiconductor region (A) of the first transistor, to the emitter of the second transistor through a second resistor, and to the emitter of the third transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |