High-reliablity single-poly eeprom cell

Claim 1

A memory device of the type used in an electrically erasable programmable read only memory array comprising a matrix of intersection bit lines and word lines having a memory device formed at intersections of the bit lines and word lines, the memory device comprising: a semiconductor substrate (20) of a first conductivity type; a first field effect transistor comprising first and second regions (22, 23) of a second conductivity type, opposite to that of the first conductivity type, formed in the substrate, the first and second regions (22, 23) being separated by a first channel region (43) formed by the substrate, and a first conductive portion (32) formed over the first channel region and separated from the first channel region by a dielectric layer (30) to provide the gate of the first field effect transistor, the first region (22) being connected to the bit line, the first conductive portion (32) being connected to the word line; a second field effect transistor comprising third and fourth regions (25,26) of the second conductivity type formed in the substrate, the third and fourth regions (25,26) being separated by a second channel region (44) formed by the substrate, the first conductive region (44) formed by the substrate, the first conductive portion (32) extending over the second channel region (44) and separated from the second channel region (44) by the dielectric layer (30) to provide the gate of the second field effect transistor; and a third field effect transistor comprising the second region (23) and a fifth region (24) of the second conductivity type formed in the substrate, the second and fifth regions (23, 24) being separated by a third channel region (45) formed by the substrate, and a second conductive portion (34) formed over the third channel region (45) to provide the gate of the third field effect transistor and extending to overlap both the second region (23) and the fourth region (26), the second conductive portion (34) being separated from the second region (23), the fourth region (26) and the third channel region (45) by the dielectric layer (30), the second conductive portion (34) including a first downwardly extending portion (36) which defines a first layer (38) of thin tunneling dielectric material between the second conductive portion (34) and the second region (23) and a second downwardly extending portion (40) which defines a second layer (42) of thin tunneling dielectric material between the second conductive portion (34) and the fourth region (26).