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Patent US4806790A successfully refreshed from Google Patents.
US4806790A
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US
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Sample-and-hold circuit
Assignee: NEC Corp
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Filing: 1988-02-12
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Granted: 1989-02-21
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Expires: 2008-02-12
Abstract
Abstract For elimination of a driftage of voltage at an output node, there is proposed a sampling-and-hold circuit comprising an n-p-n type charging transistor capable of charging up a hold-capacitor to a certain voltage level in proportion to the voltage level of an input signal, an n-p-n type driving transistor driven by the hold-capacitor for producing an output signal at a signal output node, and a clamping circuit operative to keep the voltage level of the base node of the charging transistor in a predetermined value is so far as the hold-capacitor keeps the certain voltage level, so that the hold-capacitor supplies a base current only to the driving transistor, thereby decreasing the driftage of voltage at the output node.
Inventors
- 👤 Kazuya Sone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:10
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
385 words
A sample-and-hold circuit having a sample mode and a hold mode, comprising: (a) first and second voltage lines capable of supplying voltage levels different from each other; (b) a signal input node where an input signal is supplied in said sample mode; (c) a signal output node where an output signal is supplied; (d) first, second and third nodes; (e) a first transistor having a control node coupled to said signal input node and capable of providing a conduction path between said first voltage line and said first node in said sample mode; (f) a series combination of a first constant current source and a level shifting circuit coupled between said first voltage line and said first node, said second node being provided between said first constant current source and said level shifting circuit; (g) a second transistor having a control node coupled to said second node and a capable of providing a conduction path between said first voltage line and said third node; (h) a hold-capacitor having two electrtodes one of which is coupled to said third node and the other of which is coupled to a constant voltage source, said hold-capacitor being charged up to a certain voltage level in proportion to a voltage level of said input signal for producing said output signal; (i) second and third constant current sources each having an output node coupled to said second voltage line; (j) a first switching circuit responsive to a control signal and capable of providing a conductive path between said first node and said second constant current source in said sample mode, said first switching circuit being capable of providing a conduction path between said second node and said second constant current source in said hold mode; (k) a second switching circuit responsive to said control signal and capable of providing a conduction path between said third node and said third constant current source, said second switching circuit being capable of providing a conduction path between said first voltage line and said third constant current source; and (l) voltage clamping means operative to cause said second node to have a predetermined voltage level at which said second transistor blocks said conduction path between said first voltage line and said third node in so far as said hold-capacitor keeps said certain voltage level.
Claim 2
Dependent Claim
385 words
A sample-and-hold circuit having a sample mode and a hold mode, comprising: (a) first and second voltage lines capable of supplying voltage levels different from each other; (b) a signal input node where an input signal is supplied in said sample mode; (c) a signal output node where an output signal is supplied; (d) first, second and third nodes; (e) a first transistor having a control node coupled to said signal input node and capable of providing a conduction path between said first voltage line and said first node in said sample mode; (f) a series combination of a first constant current source and a level shifting circuit coupled between said first voltage line and said first node, said second node being provided between said first constant current source and said level shifting circuit; (g) a second transistor having a control node coupled to said second node and a capable of providing a conduction path between said first voltage line and said third node; (h) a hold-capacitor having two electrtodes one of which is coupled to said third node and the other of which is coupled to a constant voltage source, said hold-capacitor being charged up to a certain voltage level in proportion to a voltage level of said input signal for producing said output signal; (i) second and third constant current sources each having an output node coupled to said second voltage line; (j) a first switching circuit responsive to a control signal and capable of providing a conductive path between said first node and said second constant current source in said sample mode, said first switching circuit being capable of providing a conduction path between said second node and said second constant current source in said hold mode; (k) a second switching circuit responsive to said control signal and capable of providing a conduction path between said third node and said third constant current source, said second switching circuit being capable of providing a conduction path between said first voltage line and said third constant current source; and (l) voltage clamping means operative to cause said second node to have a predetermined voltage level at which said second transistor blocks said conduction path between said first voltage line and said third node in so far as said hold-capacitor keeps said certain voltage level.
Claim 3
Dependent Claim
61 words
A sample-and-hold circuit as set forth in claim 1, in which said sample-and-hold circuit further comprises a third transistor having a control node coupled to said third node and capable of providing a conduction path between said first voltage line and said signal output node, and a load current source coupled between said signal output node and said second voltage line.
Claim 4
Dependent Claim
23 words
A sample-and-hold circuit as set forth in claim 2, in which said voltage clamping means comprise a diode and a constant voltage source.
Claim 5
Dependent Claim
33 words
A sample-and-hold circuit as set forth in claim 3, in which said diode is formed by a fourth transistor having a control node coupled to one end of a conduction path formed therein.
Claim 6
Dependent Claim
26 words
A sample-and-hold circuit as set forth in claim 4, in which said first, second, third and fourth transistors are formed by n-p-n type bipolar transistors, respectively.
Claim 7
Dependent Claim
27 words
A sample-and-hold circuit as set forth in claim 2, in which said voltage clamping means comprise a diode coupled between said first node and said second node.
Claim 8
Dependent Claim
33 words
A sample-and-hold circuit as set forth in claim 6, in which said diode is formed by a fourth transistor having a control node coupled to one end of a conduction path formed therein.
Claim 9
Dependent Claim
26 words
A sample-and-hold circuit as set forth in claim 7, in which said first, second, third and fourth transistors are formed by n-p-n type bipolar transistors, respectively.
Claim 10
Dependent Claim
20 words
A sample-and-hold circuit as set forth in claim 5, in which said level shifting circuit comprises a series of diodes.
Claim 11
Dependent Claim
35 words
A sample-and-hold circuit as set forth in claim 9, in which each of said series of diode is formed by an n-p-n type bipolar transistor having a base node coupled to a collector node thereof.
Claim 12
Dependent Claim
78 words
A sample-and-hold circuit as set forth in claim 10, in which said first switching circuit comprises two n-p-n type bipolar transistors alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said first node and said second constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said second node and said second constant current source.
Claim 13
Dependent Claim
79 words
A sample-and-hold circuit as set forth in claim 11, in which said second switching circuit comprises two n-p-n type bipolar transistor alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said third node and said third constant current course, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said first voltage line and said third constant current source.
Claim 14
Dependent Claim
28 words
A sample-and-hold circuit as set forth in claim 12, in which all of said n-p-n type bipolar transistors have respective forwardly biassing voltage approximately equal to one another.
Claim 15
Dependent Claim
20 words
A sample-and-hold circuit as set forth in claim 8, in which said level shifting circuit comprises a series of diodes.
Claim 16
Dependent Claim
35 words
A sample-and-hold circuit as set forth in claim 14, in which each of said series of diode is formed by an n-p-n type bipolar transistor having a base node coupled to a collector node thereof.
Claim 17
Dependent Claim
78 words
A sample-and-hold circuit as set forth in claim 15, in which said first switching circuit comprises two n-p-n type bipolar transistors alternatively shifting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said first node and said second constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said second node and said second constant current source.
Claim 18
Dependent Claim
79 words
A sample-and-hold circuit as set forth in claim 16, in which said second switching circuit comprises two n-p-n type bipolar transistors alternatively shfiting between an on-state and an off-state, one of said n-p-n type bipolar transistors being capable of providing a conduction path between said third node and said third constant current source, the other of said n-p-n type bipolar transistors being capable of providing a conduction path between said first voltage line and said third constant current source.
Claim 19
Dependent Claim
28 words
A sample-and-hold circuit as set forth in claim 17, in which all of said n-p-n type bipolar transistors have respective forwardly biassing voltage approximately equal to one another.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |