US4806788A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit with decreased burn-in time
Assignee: Mitsubishi Electric Corp
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Filing: 1987-07-06
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Granted: 1989-02-21
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Expires: 2007-07-06
Abstract
Abstract A semiconductor integrated circuit is provided with an internal voltage generator to normally operate with internal source voltage which is lower than externally supplied source voltage and serves as operating source voltage. The semiconductor integrated circuit is further provided with a control circuit for controlling an internal source voltage generator so that voltage generated by the internal source voltage generator in burn-in or the like serves as first voltage which is higher than normal internal source voltage to accelerate the burn-in.
Inventors
- 👤 Youichi Tobita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:36
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A semiconductor integrated circuit comprising a main circuit operative in first and second modes of operation and having an external power terminal for receiving an externally supplied voltage source, at least one external input terminal connected to said main circuit for receiving an externally supplied master signal, said semiconductor integrated circuit further comprising: an internal voltage source, said internal voltage source supplying a voltage that is lower than said external source voltage supplied to said external power terminal; a control circuit activated in response to said master signal to generate a control signal, said control signal having first and second states corresponding, respectively, to said first and second modes of operation of said main circuit; and an internal power circuit connected to said external power terminal and to said internal voltage source and responsive to said control signal, said internal power circuit supplying a first voltage lower than said external source voltage to said main circuit in response to said control signal in said first state, and supplying a second voltage higher than said first voltage to said main circuit in response to said control signal in said second state.
Claim 2
Dependent Claim
190 words
A semiconductor integrated circuit comprising a main circuit operative in first and second modes of operation and having an external power terminal for receiving an externally supplied voltage source, at least one external input terminal connected to said main circuit for receiving an externally supplied master signal, said semiconductor integrated circuit further comprising: an internal voltage source, said internal voltage source supplying a voltage that is lower than said external source voltage supplied to said external power terminal; a control circuit activated in response to said master signal to generate a control signal, said control signal having first and second states corresponding, respectively, to said first and second modes of operation of said main circuit; and an internal power circuit connected to said external power terminal and to said internal voltage source and responsive to said control signal, said internal power circuit supplying a first voltage lower than said external source voltage to said main circuit in response to said control signal in said first state, and supplying a second voltage higher than said first voltage to said main circuit in response to said control signal in said second state.
Claim 3
Dependent Claim
69 words
A semiconductor integrated circuit in accordance with claim 1, wherein said external signal input terminal is supplied with a master signal of a level within a prescribed normal operating range when said main circuit is in said normal operation and said control circuit is activated when the level of said master signal supplied to said external input terminal is within a prescribed range out of said normal operating range.
Claim 4
Dependent Claim
46 words
A semiconductor integrated circuit in accordance with claim 2, wherein a plurality of said external input terminals are provided and said control circuit is activated only when the levels of master signals supplied to said plurality of external input terminals are simultaneously in respective prescribed ranges.
Claim 5
Dependent Claim
18 words
A semiconductor integrated circuit in accordance with claim 2, wherein said prescribed range do not overlap each other.
Claim 6
Dependent Claim
130 words
A semiconductor integrated circuit in accordance with claim 1, wherein said internal power circuit includes an insulated gate field effect transistor (6) provided between said external power terminal and a source voltage terminal (2) of said main circuit and having a gate and a threshold voltage, said internal source voltage being provided by subtracting said threshold voltage from voltage applied to said gate of said insulated gate field effect transistor, said semiconductor integrated circuit further including boosting means coupled to said gate of said insulated gate field effect transistor for bootstrapping the gate voltage of said insulated gate field effect transistor to drive said insulated gate field effect transistor in a voltage variable resistance region so that a drop of said threshold voltage is not included in said first voltage.
Claim 7
Dependent Claim
50 words
A semiconductor integrated circuit in accordance with claim 1, wherein said control circuit comprises a plurality of insulated gate field effect transistors (N l to N n ) serially connected between said external input terminal and a ground potential, said plurality of insulated gate field effect transistors being diode-connected respectively.
Claim 8
Dependent Claim
52 words
A semiconductor integrated circuit in accordance with claim 1, wherein said control circuit comprises a plurality of insulated gate field effect transistors (L l to L l ) connected in series between said external input terminal and said external power terminal, said plurality of insulated gate field effect transistors being diode-connected respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |