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US4806457A
Expired / Lapsed
US
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Method of manufacturing integrated circuit semiconductor device
Assignee: NEC Electronics Corp
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Filing: 1987-04-09
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Granted: 1989-02-21
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Expires: 2007-04-09
Abstract
Abstract A method of manufacturing integrated circuit semiconductor device in which a check pattern of resist film is formed for monitoring a state of an element-forming resist pattern having a narrow interval of 1.0 μm or less is disclosed. The check pattern is designed such that a plurality of resist stripes are arranged with intervals therebetween. Each of the intervals is of 1.0 μm or less and the width of the resist stripe is three times or more the interval.
Inventors
- 👤 Masayuki Yanagisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:12
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70625; G03F7/20; H; H10; H10W; H10W46/00; H10W46/601
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
101 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that at least three resist stripes are arranged in parallel with interposing intervals, said intervals having different widths of 1μm or less, and each of said resist stripes having a width of three times or more the maximum width of said intervals and a length of ten times or more the maximum width of said intervals.
Claim 2
Independent Claim
101 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that at least three resist stripes are arranged in parallel with interposing intervals, said intervals having different widths of 1μm or less, and each of said resist stripes having a width of three times or more the maximum width of said intervals and a length of ten times or more the maximum width of said intervals.
Claim 3
Dependent Claim
25 words
A method of claim 1, in which said resist stripes are four or more in number and widths of the intervals therebetween are successively reduced.
Claim 4
Dependent Claim
20 words
A method of claim 1, in which all of said resist stripes have the same width and the same length.
Claim 5
Independent Claim
95 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a pair of resist stripes extend with interposing a narrow interval therebetween, said interval being divided at least three sections having different widths of 1μm or less, and each of said stripes having a width of three times or more the maximum width of said sections of said interval
Claim 6
Independent Claim
95 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a pair of resist stripes extend with interposing a narrow interval therebetween, said interval being divided at least three sections having different widths of 1μm or less, and each of said stripes having a width of three times or more the maximum width of said sections of said interval
Claim 7
Independent Claim
126 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that first and second resist stripes extend in parallel with interposing an interval having a constant width of 1 μm or less each of said first and second resist stripes being constituted by a plurality of portions each having different width, the width of one group of said portions being three times or more said constant width of said interval and the width of the other group of said portions being less than three times said constant width of said interval.
Claim 8
Independent Claim
126 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that first and second resist stripes extend in parallel with interposing an interval having a constant width of 1 μm or less each of said first and second resist stripes being constituted by a plurality of portions each having different width, the width of one group of said portions being three times or more said constant width of said interval and the width of the other group of said portions being less than three times said constant width of said interval.
Claim 9
Independent Claim
105 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a plurality of resist stripes having different widths are arranged with interposing intervals having a constant width of 1 μm or less, and the minimum width of said stripes being less than three times said constant width of said interval and the maximum width of said stripes being not less than three times said constant width of said interval.
Claim 10
Independent Claim
105 words
A method of manufacturing an integrated circuit semiconductor device comprising a step of patterning a resist film by photolithographic technique to form an element-forming resist pattern and a check pattern for monitoring a state of said element-forming resist pattern, said check pattern being designed such that a plurality of resist stripes having different widths are arranged with interposing intervals having a constant width of 1 μm or less, and the minimum width of said stripes being less than three times said constant width of said interval and the maximum width of said stripes being not less than three times said constant width of said interval.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |