Patent US4804929A successfully refreshed from Google Patents.
US4804929A
Expired / Lapsed
US
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Control pulse generator
Assignee: Toshiba Corp
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Filing: 1987-09-28
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Granted: 1989-02-14
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Expires: 2007-09-28
Abstract
Abstract A control pulse generator according to the present invention includes a voltage generator for generating an output voltage proportional to a power supply voltage, an inverter for generating an inversion signal whose signal level is inverted when the output voltage from the voltage generator reaches a predetermined value, and a pulse signal generator for delaying a level inversion timing of the inversion signal by a predetermined delay time, and generating a control pulse having a width corresponding to the delay time. According to the control pulse generator with the above arrangement, the width of the control pulse can be determined on the basis of the delay time of the pulse signal generator, regardless of rise states of the power supply voltage. In addition, the height of the control pulse can be set at a desired value according to a supply voltage to the pulse signal generator, regardless of rise states of the supply voltage.
Inventors
- 👤 Hideo Kato
- 👤 Hiroshi Iwahashi
- 👤 Masamichi Asano
- 👤 Akira Narita
- 👤 Shinichi Kikuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:37
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03L; H03L1/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
141 words
A control pulse generator for a semiconductor integrated circuit, comprising: voltage generating means for generating an output voltage proportional to a power supply voltage which is applied to the semiconductor integrated circuit; inverting means for generating an inversion signal, said inversion signal having an inverted level when the value of said output voltage reaches a predetermined voltage value; and pulse signal generating means for delaying the occurrence of said inversion signal by a predetermined delay time, for generating a control pulse having a width corresponding to said predetermined delay time, and for supplying said control pulse to an internal circuit of said semiconductor integrated circuit, wherein the voltage generating means includes voltage holding means for holding the value of the output voltage from said voltage generating means at a constant level in response to the signal level of said control pulse.
Claim 2
Dependent Claim
141 words
A control pulse generator for a semiconductor integrated circuit, comprising: voltage generating means for generating an output voltage proportional to a power supply voltage which is applied to the semiconductor integrated circuit; inverting means for generating an inversion signal, said inversion signal having an inverted level when the value of said output voltage reaches a predetermined voltage value; and pulse signal generating means for delaying the occurrence of said inversion signal by a predetermined delay time, for generating a control pulse having a width corresponding to said predetermined delay time, and for supplying said control pulse to an internal circuit of said semiconductor integrated circuit, wherein the voltage generating means includes voltage holding means for holding the value of the output voltage from said voltage generating means at a constant level in response to the signal level of said control pulse.
Claim 3
Dependent Claim
49 words
A generator according to claim 1, wherein said power supply voltage generating means includes: a plurality of MOS transistors of the same conductivity type respectively formed in well regions isolated from each other, source electrodes of said plurality of MS transistors being independently connected to said well regions, respectively.
Claim 4
Dependent Claim
53 words
A control pulse generator for a semiconductor integrated circuit according to claim 1, wherein said voltage generating means includes a plurality of MOS transistors of the same conductivity type formed in well regions isolated from each other, the source electrodes of said plurality of MS transistors being independently connected to said well regions.
Claim 5
Dependent Claim
45 words
A control pulse generator for a semiconductor circuit as in claim 1, wherein the initial power supply voltage of said internal circuit to be initialized by said control pulse corresponds to the power supply voltage level at which the inversion of said inversion signal occurs.
Claim 6
Dependent Claim
49 words
A generator according to claim 4, wherein said power supply voltage generating means includes: a plurality of MOS transistors of the same conductivity type respectively formed in well regions isolated from each other, source electrodes of said plurality of MOS transistors being independently connected to said well regions, respectively.
Claim 7
Dependent Claim
144 words
A control pulse generator for a semiconductor integrated circuit, comprising: voltage generating means for generating an output voltage proportional to a power supply voltage supplied to the semiconductor integrated circuit; inverting means for generating an inversion signal, said inversion signal having an inverted level when the value of said output voltage reaches a predetermined voltage value; and pulse signal generating means for delaying the occurrence of said inversion signal by a predetermined delay time, for generating a control pulse having a width corresponding to said predetermined delay time, and for supplying said control pulse to an internal circuit of a semiconductor integrated circuit, wherein said pulse generating means includes a plurality of cascade-connected CMOS inverters and a plurality of capacitors, respectively connected to the output terminals of said plurality of CMOS inverters, for setting the initial output potential of each of said CMOS inverters.
Claim 8
Dependent Claim
144 words
A control pulse generator for a semiconductor integrated circuit, comprising: voltage generating means for generating an output voltage proportional to a power supply voltage supplied to the semiconductor integrated circuit; inverting means for generating an inversion signal, said inversion signal having an inverted level when the value of said output voltage reaches a predetermined voltage value; and pulse signal generating means for delaying the occurrence of said inversion signal by a predetermined delay time, for generating a control pulse having a width corresponding to said predetermined delay time, and for supplying said control pulse to an internal circuit of a semiconductor integrated circuit, wherein said pulse generating means includes a plurality of cascade-connected CMOS inverters and a plurality of capacitors, respectively connected to the output terminals of said plurality of CMOS inverters, for setting the initial output potential of each of said CMOS inverters.
Claim 9
Dependent Claim
97 words
A generator according to claim 6, wherein one of said plurality of capacitors is connected between an output terminal of a first one of said plurality of CMOS inverters and a first power supply circuit of the semiconductor integrated circuit, and another capacitor of said plurality of capacitors is connected between an output terminal of a second one of said plurality of CMOS inverters and a second power supply circuit of the semiconductor integrated circuit, a difference in potential between said first power supply circuit and said second power supply circuit corresponding to said power supply voltage.
Claim 10
Dependent Claim
49 words
A generator according to claim 6, wherein said power supply voltage generating means includes: a plurality of MOS transistors of the same conductivity type respectively formed in well regions isolated from each other, source electrodes of said plurality of MOS transistors being independently connected to said well regions, respectively.
Claim 11
Dependent Claim
49 words
A generator according to claim 6, wherein said power supply voltage generating means includes: a plurality of MOS transistors of the same conductivity type respectively formed in well regions isolated from each other, source electrodes of said plurality of MOS transistors being independently connected to said well regions, respectively.
Claim 12
Dependent Claim
131 words
A control pulse generator for a semiconductor integrated circuit, comprising: first generator means for generating an output voltage which is proportional to a power supply voltage applied to said semiconductor integrated circuit; a capacitor, coupled to said first generator means, for setting an initial state of said output voltage; second generator means, coupled to said first generator means, for generating an inversion signal, said inversion signal having an inverted output level when the value of said output voltage reaches a prescribed voltage level; and circuit means coupled to said second generator means for delaying said inversion signal by a prescribed delay time, for generating a control pulse having a width corresponding to said prescribed delay time, and for supplying said control pulse to an internal circuit of the semiconductor integrated circuit.
Claim 13
Dependent Claim
131 words
A control pulse generator for a semiconductor integrated circuit, comprising: first generator means for generating an output voltage which is proportional to a power supply voltage applied to said semiconductor integrated circuit; a capacitor, coupled to said first generator means, for setting an initial state of said output voltage; second generator means, coupled to said first generator means, for generating an inversion signal, said inversion signal having an inverted output level when the value of said output voltage reaches a prescribed voltage level; and circuit means coupled to said second generator means for delaying said inversion signal by a prescribed delay time, for generating a control pulse having a width corresponding to said prescribed delay time, and for supplying said control pulse to an internal circuit of the semiconductor integrated circuit.
References Cited (Backward Citations)
US3806741A
Cited
JPS61150515A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |