US4804635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacture of galluim arsenide field effect transistors
Assignee: TE Connectivity Solutions GmbH
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Filing: 1985-03-11
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Granted: 1989-02-14
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Expires: 2005-03-11
Abstract
Abstract A self-aligned gate structure for a compound semiconductor MESFET is formedrom a lower silicon layer and an upper metal, e.g. nickel, region. The nickel region forms an etch mask for the silicon and subsequently an implantation mask for the drain and source regions. Etching of the silicon provides an undercut whereby the gate separation from the drain and source is defined. Heating the structure to anneal the implant diffuses the metal into the silicon to form a compound silicide gate structure.
Inventors
- 👤 John M. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D64/00; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
91 words
A process for fabricating a field effect transistor including: providing a semiconductor substrate having a layer of silicon deposited on one major surface thereof; selectively depositing a metal on said surface to define a transistor gate area; implanting drain and source regions using the metal as a mask to define the gate/drain and gate/source spacing; removing the exposed silicon and undercutting the metal; and heating the assembly whereby the implanted regions are annealed and activated and whereby simultaneously the metal diffuses into the remaining silicon to form a metal silicide gate.
Claim 2
Dependent Claim
91 words
A process for fabricating a field effect transistor including: providing a semiconductor substrate having a layer of silicon deposited on one major surface thereof; selectively depositing a metal on said surface to define a transistor gate area; implanting drain and source regions using the metal as a mask to define the gate/drain and gate/source spacing; removing the exposed silicon and undercutting the metal; and heating the assembly whereby the implanted regions are annealed and activated and whereby simultaneously the metal diffuses into the remaining silicon to form a metal silicide gate.
References Cited (Backward Citations)
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US4180596A
Cited
US4425700A
Cited
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |