Reset and synchronization interface circuit

Claim 2

A rest and circuit synchronization interface circuit for use in a subscriber power controller comprising: resetting means including first comparator means, second comparator means, and network means generating a reset signal at a first node; said first comparator means being formed of first comparator having hysteresis for comparing an input signal with a reference voltage to produce a first output signal; said second comparator means being formed of a second comparator for comparing the first output signal from the first comparator with the reference voltage to produce a second output signal; said network means being responsive to the second signal for inverting and shifting the level of the second output signal to produce the reset signal; synchronizing means including a third comparator means and an AND logic gate for generating a modified synchronizing signal at a second node; said third comparator means being formed of a third comparator for inverting of a synchronizing clock signal to generate a complementary synchronizing clock signal; and said logic gate combining logically the first output signal from said first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

Claim 3

A reset and synchronization interface circuit as claimed in claim 1 wherein said first comparator comprises a first differential amplifier formed of a pair of transistors whose bases are connected to the input signal and the reference voltage.

Claim 4

A reset and synchronization interface circuit as claimed in claim 2, wherein said second comparator comprises a second differential amplifier formed of a pair of transistors whose bases are connected to the output of said first comparator and the reference voltage.

Claim 5

A reset and synchronization interface circuit as claimed in claim 3, wherein said network means comprises a current mirror arrangement and a push-pull output stage.

Claim 6

A reset and synchronization interface circuit as claimed in claim 4, wherein said third comparator comprises a third differential amplifier formed of a pair of transistors whose bases are connected to the synchronizing clock signal and a bias voltage.

Claim 7

A reset and synchronization interface circuit as claimed in claim 5, wherein said AND logic gate comprise an ECL circuit formed of an input transistor, a reference transistor, and a current source.

Claim 8

A reset and synchronization interface circuit as claimed in claim 1, wherein said reset signal is normally a low voltage level and is changed to a high voltage level corresponding to a positive pulse in response to the input signal being lower than the reference voltage.

Claim 9

A reset and synchronization interface circuit as claimed in claim 7, wherein said first output signal from said first comparator is a complement of the reset signal which is used to disable the AND logic gate when there is a low voltage detected so as to prevent the synchronizing clock signal from reaching the second output node.

Claim 10

In a subscriber power controller device for converting a high voltage at an S interface into a stable, regulated low voltage to be used by integrated circuits in an ISDN terminal equipment, said controller device including resetting and synchronization means for resetting a digital subscriber controller, a microprocessor and other integrated circuits in the terminal equipment and for synchronizing an internal free-running oscillator to be in synchronism with an external clock signal in the other integrated circuits, said resetting and synchronizing means comprising: resetting means including first comparator means, second comparator means, and network means generating a reset signal at a first node; said first comparator means being formed of first comparator having hysteresis for comparing an input signal with a reference voltage to produce a first output signal; said second comparator means being formed of a second comparator for comparing the first output signal from the first comparator with the reference voltage to produce a second output signal; said network means being responsive to the second signal for inverting and shifting the level of the second output signal to produce the reset signal; synchronizing means including a third comparator means and an AND logic gate for generating a modified synchronizing signal at a second node; said third comparator means being formed of a third comparator for inverting of a synchronizing clock signal to generate a complementary synchronizing clock signal; and said logic gate combining logically the first output signal from said first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

Claim 11

In a subscriber power controller device for converting a high voltage at an S interface into a stable, regulated low voltage to be used by integrated circuits in an ISDN terminal equipment, said controller device including resetting and synchronization means for resetting a digital subscriber controller, a microprocessor and other integrated circuits in the terminal equipment and for synchronizing an internal free-running oscillator to be in synchronism with an external clock signal in the other integrated circuits, said resetting and synchronizing means comprising: resetting means including first comparator means, second comparator means, and network means generating a reset signal at a first node; said first comparator means being formed of first comparator having hysteresis for comparing an input signal with a reference voltage to produce a first output signal; said second comparator means being formed of a second comparator for comparing the first output signal from the first comparator with the reference voltage to produce a second output signal; said network means being responsive to the second signal for inverting and shifting the level of the second output signal to produce the reset signal; synchronizing means including a third comparator means and an AND logic gate for generating a modified synchronizing signal at a second node; said third comparator means being formed of a third comparator for inverting of a synchronizing clock signal to generate a complementary synchronizing clock signal; and said logic gate combining logically the first output signal from said first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

Claim 12

In a reset and synchronization interface circuit as claimed in claim 9 where in said first comparator comprises a first differential amplifier formed of a pair of transistors whose bases are connected to the input signal and the reference voltage.

Claim 13

In a reset and synchronization interface circuit as claimed in claim 10, wherein said second comparator comprises a second differential amplifier formed of a pair of transistors whose bases are connected to the output of said first comparator and the reference voltage.

Claim 14

In a reset and synchronization interface circuit as claimed in claim 11, wherein said network means comprises a current mirror arrangement and a push-pull output stage.

Claim 15

In a reset and synchronization interface circuit as claimed in claim 12, wherein said third comparator comprises a third differential amplifier formed of a pair of transistors whose bases are connected to the synchronizing clock signal and a bias voltage.

Claim 16

In a reset and synchronization interface circuit as claimed in claim 13, wherein said AND logic gate comprise an ECL circuit formed of an input transistor, a reference transistor, and a current source.

Claim 17

In a reset and synchronization interface circuit as claimed in claim 9, wherein said reset signal is normally a low voltage level and is changed to a high voltage level corresponding to a positive pulse in response to the input signal being lower than the reference voltage.

Claim 18

In a reset and synchronization interface circuit as claimed in claim 15, wherein said first output signal from said first comparator is a complement of the reset signal which is used to disable the AND logic gate when there is a low voltage detected so as to prevent the synchronizing clock signal from reaching the second output node.