US4803662A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EEPROM cell
Assignee: Sharp Corp
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Filing: 1986-08-15
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Granted: 1989-02-07
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Expires: 2006-08-15
Abstract
Abstract An EEPROM cell for a memory device comprises a pair of bit lines each including a floating-gate MOS transistor such that a selected one of the transistors can be charged while the other is in uncharged condition by applying a higher voltage to a corresponding one of the bit lines and a lower voltage to the other bit line. Information stored in such a cell can thus be rewritten simply by applying a high voltage to one of the pair of its bit lines without carrying out a time-consuming ERASE mode of operation.
Inventors
- 👤 Kenichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:15
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
An EEPROM cell for a memory device comprising a pair of floating-gate transistors consisting of a first memory transistor and a second memory transistor, and a pair of bit lines consisting of a first bit line corresponding to said first memory transistor and a second bit line corresponding to said second memory transistor, each of said floating-gate transistors having a floating gate and a control gate, the floating gate of said first floating-gate transistor being coupled to said first bit line, the floating gate of said second floating-gate transistor being coupled to said second bit line, the control gate of said first floating-gate transistor being connected to said second bit line and the control gate of said second floating-gate transistor being connected to said first bit line, wherein information stored in said cell is determined by detecting which of said memory transistors has a floating-gate in charged condition and which in uncharged condition, and application of a higher voltage on one of said bit lines and a lower voltage to the other of said bit lines causes one of said memory transistors to be in charged condition and the other of said memory transistors to be in uncharged condition.
Claim 2
Dependent Claim
199 words
An EEPROM cell for a memory device comprising a pair of floating-gate transistors consisting of a first memory transistor and a second memory transistor, and a pair of bit lines consisting of a first bit line corresponding to said first memory transistor and a second bit line corresponding to said second memory transistor, each of said floating-gate transistors having a floating gate and a control gate, the floating gate of said first floating-gate transistor being coupled to said first bit line, the floating gate of said second floating-gate transistor being coupled to said second bit line, the control gate of said first floating-gate transistor being connected to said second bit line and the control gate of said second floating-gate transistor being connected to said first bit line, wherein information stored in said cell is determined by detecting which of said memory transistors has a floating-gate in charged condition and which in uncharged condition, and application of a higher voltage on one of said bit lines and a lower voltage to the other of said bit lines causes one of said memory transistors to be in charged condition and the other of said memory transistors to be in uncharged condition.
Claim 3
Dependent Claim
13 words
The EEPROM cell of claim 1 wherein said memory transistors are MOS transistors.
Claim 4
Dependent Claim
24 words
The EEPROM cell of claim 1 wherein said first memory transistor becomes charged if said higher voltage is applied to said second bit line.
Claim 5
Dependent Claim
43 words
The EEPROM cell of claim 1 wherein said first bit line includes a first select transistor and said second bit line includes a second select transistor, the gates of said first and second select transistors are connected in common to a word line.
Claim 6
Dependent Claim
59 words
The EEPROM cell of claim 4 wherein the source of said first select transistor is connected to the drain of said first memory transistor and to the gate of said second memory transistor, and the source of said second select transistor is connected to the drain of said second memory transistor and the gate of said first memory transistor.
Claim 7
Dependent Claim
17 words
The EEPROM cell of claim 1 wherein each of said bit lines is grounded at one end.
Claim 8
Dependent Claim
15 words
The EEPROM cell of claim 1 wherein each of said memory transistors has two-level structure.
Claim 9
Dependent Claim
15 words
The EEPROM cell of claim 1 wherein each of said memory transistors has three-level structure.
Claim 10
Dependent Claim
59 words
The EEPROM cell of claim 1 further comprising a first cutoff transistor connected to said first bit line and having a control gate connected to the control gate of said first floating-gate transistor, and a second cutoff transistor connected to said second bit line and having a control gate connected to the control gate of said second floating-gate transistor.
References Cited (Backward Citations)
US4467451A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |