Serial first-in-first-out (FIFO) memory and method for clocking the same

Claim 1

An improvement in a serial FIFO memory comprising a plurality of insulated-gate field-effect transistors of the same conductivity and control type, each having an input and output, said plurality of transistors being arranged and configured into n signal branches (z 1 . . . z n ), each with m cells, which comprise parallel signal paths, the inputs thereof being coupled to a signal input (s e ) of said memory and the outputs thereof being coupled to a signal output (s a ) of said memory, each signal branch comprising m transfer transistors, each having a source-drain section arranged in a series signal path for transmitting therethrough input signals having a predetermined data rate, a gate of each of the transfer transistors in each signal branch being supplied with clock signals whose effective pulses, in direction from the m-th to the first transfer transistor in each branch, are in such a timely succession that the transistors are rendered conductive one at a time in turn, said improvement comprising: wherein said memory exclusively serves as a memory for digital signals; wherein the number of clock signals equals n, and their repetition rate equals one n-th of said data rate of said input signals; wherein of said m transfer transistors in each signal branch: in the first signal branch (z 1 ), the first, the (n+1)th, the (2n+1)th, . . . , and the (qn+1)th transfer transistors are clocked by the n-th clock signal (s n ), the second, the (n+2)th, the (2n+2)th, . . . , and the (qn+2)th transfer transistors are clocked by the (n-1)th clock signal (s n-1 ), and so forth in an identical pattern for each remaining transfer transistor and clock signal until the n-th, the 2n-th, the 3n-th, . . . , and the qn-th transfer transistors are clocked by the first clock signal (s 1 ), in the second signal branch (x 2 ) the first, the (n+1)th, the (2n+1)th, . . . , and the (qn+1)th transfer transistors are clocked by the (n-1)th clock signal (s n-1 ), the second, the (n+2)th, the (2n+2)th, . . . , and the (qn+2)th transfer transistors are clocked by the (n=2)th clock signal and so forth in an identical pattern for each remaining transfer transistor and clock signal until the n-th, the 2n-th, the 3n-th, . . . , and the qn-th transfer transistors are clocked by the n-th clock signal, and continuing in an identical pattern for each remaining signal branch until in the last signal branch (z n ) the first, the (n+1)th, the (2n+1)th, . . . , and the (qn+1)th transfer transistors are clocked by the first clock signal (s 1 ), the second, the (n+2)th, the (2n+2)th, . . . , and the (qn+2)th transfer transistors are clocked by the n-th clock signal (s n ), and so forth in an identical pattern for each remaining transfer transistor and clock signal until the n-th, the 2n-th, the 3n-th, . . . , and the qn-th transfer transistors are clocked by the second clock signal, with q indicating the number of complete blocks consisting of n times n transfer transistors as counted from the signal input, and where in each signal branch, a level generator (p) is connected to the output of the source-drain section of each transfer transistor except the m-th one; and wherein said inputs of said signal branches are directly applied to said signal input (s e ) and said outputs thereof are directly applied to said signal output (s a ).