Patent US4803612A successfully refreshed from Google Patents.
US4803612A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock ripple reduction in a linear low dropout C/DMOS regulator
Assignee: National Semiconductor Corp
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Filing: 1988-06-08
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Granted: 1989-02-07
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Expires: 2008-06-08
Abstract
Abstract A pair of voltage triplers are formed in a C/DMOS circuit along with a self-isolated DMOS transistor. The voltage triplers are driven in phase opposition from the system clock and their outputs commonly drive the gate of the DMOS transistor which acts as the pass element in a voltage regulator. A control circuit includes a reference voltage generator and a differential amplifier that senses a fraction of the d-c output voltage. The amplifier has an output coupled to the DMOS gate thereby to create a stabilizing negative feedback loop. The voltage triplers overdrive the DMOS transistor so the dropout voltage is low and the full wave rectifier action will double the clock frequency for easier filtering.
Inventors
- 👤 Timothy J. Skovmand
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:42
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/575; H; H03; H03K; H03K17/00; H03K17/06; H03K17/063
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
134 words
A C/DMOS voltage regulator connectable to a source of operating power and to a source of clock pulses for producing a regulated d-c output, said voltage regulator comprising: a DMOS pass transistor having a gate electrode, its drain electrode coupled to said source of operating power and its source electrode providing said regulated d-c output; a first voltage multiplier rectifier having an input coupled to receive said source of clock pulses and an output coupled to said gate of said DMOS transistor; a second voltage multiplier rectifier having an input coupled to receive the complement of said source of clock pulses and an output coupled to said gate of said DMOS transistor; and a control circuit responsive to said d-c output and operative to control the potential of said gate of said DMOS transistor.
Claim 2
Dependent Claim
134 words
A C/DMOS voltage regulator connectable to a source of operating power and to a source of clock pulses for producing a regulated d-c output, said voltage regulator comprising: a DMOS pass transistor having a gate electrode, its drain electrode coupled to said source of operating power and its source electrode providing said regulated d-c output; a first voltage multiplier rectifier having an input coupled to receive said source of clock pulses and an output coupled to said gate of said DMOS transistor; a second voltage multiplier rectifier having an input coupled to receive the complement of said source of clock pulses and an output coupled to said gate of said DMOS transistor; and a control circuit responsive to said d-c output and operative to control the potential of said gate of said DMOS transistor.
Claim 3
Dependent Claim
23 words
The voltage regulator of claim 1 wherein said first and second voltage multiplier rectifiers are voltage triplers and are composed of CMOS devices.
Claim 4
Dependent Claim
49 words
The voltage regulator of claim 1, including a voltage reference producing circuit and differential amplifier means having an output coupled to said gate of said DMOS transistor, a first input coupled to said reference producing circuit and a second input coupled to receive a fraction of said d-c output.
Claim 5
Dependent Claim
60 words
The voltage regulator of claim 3 wherein said differential amplifier means include an inverting CMOS amplifier stage having an output connected to said gate of said DMOS transistor, an input coupled to a differential driver having its inverting input connected to said reference voltage and its non-inverting input connected to a voltage divider that is connected across said d-c output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |