IGT and MOSFET devices having reduced channel width

Abstract

Abstract During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on. Retardation of lateral channel growth just below the substrate surface results in an insulated gate device of reduced channel length and improved transconductance. In a preferred embodiment, the slow-diffusing drain-forming dopant is implanted on the substrate surface together with a fast-diffusing drain-forming dopant, and the latter is diffused to a pinch off depth below the substrate surface to counteract pinch off resistance between opposed segments of an adjacent shallow channel-forming well.

Inventors

• 👤 Mike F. Chang
• 👤 Hamza Yilmaz
• 👤 George L. Gauffreau
• 👤 King Owyang

Bibliographic Details