Method of forming interconnections and crossings between metallization levels of an integrated circuit

Claim 1

A method of forming interconnections and crossings between metallization levels of an integrated circuit, in which a first metallization level having a thickness e m1 has been formed on a substrate during an initial sequence a by means of etching or "lift-off" techniques generally used, characterized in that after the said initial sequence a resulting in that the said first metallization level is obtained, the inversion of a relief at the level of an interconnection is obtained by isotropic deposition, planarization by means of a sacrificial layer and anisotropic selective etching with respect to the said sacrificial layer according to the following further steps: b. deposition of a first isolating layer having a thickness e i1 constituting the isolation between the said metallization level and the metallization level immediately above it, c. deposition of a second isolating layer having a thickness e i2 constituting a phantom mask which will permit of ensuring the isolation by the said first layer at the levels of the crossings of the metallizations, d. etching of the isolation pattern of the said second isolating layer selectively with respect to the first layer, e. planarization of the structure thus obtained by the use of a sacrificial layer, f. etching of the said sacrificial layer down to the level of the second isolating layer, g. etching of the structure thus obtained so that the respective etching rates R 1 , R 2 and R S of the said first, second and sacrificial layers, respectively, permit of merging at the first level of metallization, while at the same time the said second isolating layer having a thickness e i2 is partly or entirely etched on the surface of the said structure, the relief of the said first metallization level and the inversion of a relief at the areas of the interconnections resulting from a selective etching of the first isolating layer with respect to the sacrificial layer, which ensures the self-alignment of the etching of the said first isolating layer at the first metallization level without any specific photolithographic step, h. formation of the said metallization level lying immediately above it.

Claim 2

A method of forming interconnections and crossings between metallization levels of an integrated circuit, in which a first metallization level having a thickness e m1 has been formed on a substrate during an initial sequence a by means of etching or "lift-off" techniques generally used, characterized in that after the said initial sequence a resulting in that the said first metallization level is obtained, the inversion of a relief at the level of an interconnection is obtained by isotropic deposition, planarization by means of a sacrificial layer and anisotropic selective etching with respect to the said sacrificial layer according to the following further steps: b. deposition of a first isolating layer having a thickness e i1 constituting the isolation between the said metallization level and the metallization level immediately above it, c. deposition of a second isolating layer having a thickness e i2 constituting a phantom mask which will permit of ensuring the isolation by the said first layer at the levels of the crossings of the metallizations, d. etching of the isolation pattern of the said second isolating layer selectively with respect to the first layer, e. planarization of the structure thus obtained by the use of a sacrificial layer, f. etching of the said sacrificial layer down to the level of the second isolating layer, g. etching of the structure thus obtained so that the respective etching rates R 1 , R 2 and R S of the said first, second and sacrificial layers, respectively, permit of merging at the first level of metallization, while at the same time the said second isolating layer having a thickness e i2 is partly or entirely etched on the surface of the said structure, the relief of the said first metallization level and the inversion of a relief at the areas of the interconnections resulting from a selective etching of the first isolating layer with respect to the sacrificial layer, which ensures the self-alignment of the etching of the said first isolating layer at the first metallization level without any specific photolithographic step, h. formation of the said metallization level lying immediately above it.

Claim 4

A method as claimed in any one of claims 1 or 2, characterized in that the said first isolating layer may be a single layer or a double layer.

Claim 5

A method as claimed in any one of claims 1 or 2, characterized in that the said depositions of isolating layers are isotropic.

Claim 6

A method as claimed in any one of claims 1 or 2, characterized in that the selective etching of an isolating layer with respect to another such layer is obtained.

Claim 7

A method as claimed in any one of claims 1 or 2, characterized in that the said sacrificial layer is constituted, by a resin or a polyimide.

Claim 8

A method as claimed in any one of claims 1 or 2, characterized in that the etching conditions are given by relations between the various metal and isolation thicknesses on the one hand and the corresponding etching rates in the various dielectric isolation materials on the other hand.

Claim 9

A method as claimed in any one of claims 1 or 2, characterized in that the choice of a sufficient thickness e i2 permits maintaining a double layer of isolation dielectric materials, which improves the reliability and the efficiency of the integrated circuit.