US4802168A
Expired / Lapsed
US
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Test signal generating circuit
Assignee: Ando Electric Co Ltd
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Filing: 1987-02-05
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Granted: 1989-01-31
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Expires: 2007-02-05
Abstract
Abstract A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.
Inventors
- 👤 Koyu Yamanoi
- 👤 Yoshio Yoshizakiya
- 👤 Masayoshi Dehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:18
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191; G01R31/31917; G01R31/31928
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
155 words
A test signal generating circuit, comprising: first, second, third and fourth delay units each including a gate for a predetermined input binary signal for providing an output pulse when the gate is enabled by a repetitive reference signal having a constant interval, a setting circuit for setting a pulse number corresponding to any desired delay period of time, a counter for counting clock pulses given to said counter in a number corresponding to the set number placed in the setting circuit starting from the time when said counter received said output pulse from said gate and for providing an output pulse when said number is reached; and a flip-flop having a set input terminal to which the outputs from said first and second delay units are applied and a reset input terminal to which the outputs from said third and fourth delay units are applied for obtaining a test signal at an output terminal thereof.
Claim 2
Dependent Claim
155 words
A test signal generating circuit, comprising: first, second, third and fourth delay units each including a gate for a predetermined input binary signal for providing an output pulse when the gate is enabled by a repetitive reference signal having a constant interval, a setting circuit for setting a pulse number corresponding to any desired delay period of time, a counter for counting clock pulses given to said counter in a number corresponding to the set number placed in the setting circuit starting from the time when said counter received said output pulse from said gate and for providing an output pulse when said number is reached; and a flip-flop having a set input terminal to which the outputs from said first and second delay units are applied and a reset input terminal to which the outputs from said third and fourth delay units are applied for obtaining a test signal at an output terminal thereof.
Claim 3
Dependent Claim
28 words
A test signal generating circuit according to claim 1, wherein said setting circuitry is constituted by a memory for storing a value supplied from a central processing unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |