Semiconductor memory device having serial addressing scheme

Claim 2

A semiconductor memory device comprising a memory array of memory cells arranged in rows and columns, row selecting means for selecting one of said rows, column selecting means for serially selecting said columns consecutively in synchronism with clock signals, output means for outputting data on the selected column, an external terminal, a column address detecting means for generating a detection signal when a predetermined one of said columns is selected by said column selecting means, and means for applying said detection signal to said external terminal, whereby the presence of said detection signal at said external terminal indicates that said predetermined column is selected by said column selecting means.

Claim 3

the memory according to claim 1, in which word lines are provided in said rows and a plurality pairs of bit lines are provided in said columns, in said memory array.

Claim 4

A memory according to claim 1, further comprises a plurality of data holding circuits each provided for each of said columns and operatively holding data read from a selected memory cell of its own column.

Claim 5

The memory according to claim 1, further comprises a bus line coupled to the input of said output means.

Claim 6

The memory according to claim 2, in which said column selecting means includes a plurality of transfer gates each coupled between each bit line and the input of said output means, a shift register having a plurality of stages, and drive means responsive to the output of said register means for enabling one of said transfer gates.

Claim 7

A semiconductor memory device comprising a plurality of memory locations, first means for generating address information in response to pulses, second means responsive to said address information generated by said first means for addressing one of said memory locations, third means coupled to said second means for generating a detection signal when a predetermined one of said memory location is addressed by said second means, an external terminal, and means for applying said detection signal to said external terminal.

Claim 8

A semiconductor memory device comprising a plurality of memory locations, first means for generating address information in response to pulses, second means responsive to said address information generated by said first means for addressing one of said memory locations, third means coupled to said second means for generating a detection signal when a predetermined one of said memory location is addressed by said second means, an external terminal, and means for applying said detection signal to said external terminal.

Claim 9

A semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, a row selection circuit for selecting one of said word lines, a plurality of data holding circuits each coupled to each one of said bit lines for operatively holding data on the associated bit line, a bus line, a plurality of transfer gates each coupled between each one of said data holding circuits and said bus line, an output circuit coupled to said bus line for operatively generating data on said bus line, a serial selecting circuit having a plurality of outputs each coupled to each one of said transfer gates for enabling said transfer gates sequentially, a selection detecting circuit coupled to a predetermined one of said outputs of said serial selecting circuit for generating a detection signal when said predetermined one of said outputs of said serial selecting circuit is enabled, an external terminal, and means for applying said detection signal to said external terminal.

Claim 10

A semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, a plurality of memory cells each coupled to one of said word lines and one of said bit lines, a row selection circuit for selecting one of said word lines, a plurality of data holding circuits each coupled to each one of said bit lines for operatively holding data on the associated bit line, a bus line, a plurality of transfer gates each coupled between each one of said data holding circuits and said bus line, an output circuit coupled to said bus line for operatively generating data on said bus line, a serial selecting circuit having a plurality of outputs each coupled to each one of said transfer gates for enabling said transfer gates sequentially, a selection detecting circuit coupled to a predetermined one of said outputs of said serial selecting circuit for generating a detection signal when said predetermined one of said outputs of said serial selecting circuit is enabled, an external terminal, and means for applying said detection signal to said external terminal.