US4802126A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: NEC Electronics Corp
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Filing: 1987-11-18
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Granted: 1989-01-31
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Expires: 2007-11-18
Abstract
Abstract For preventing a semiconductor substrate from undesirable discharging of electric charges, there is disclosed a semiconductor memory device fabricated on the semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of memory cells arranged in rows and columns and having read only memory cells and random access memory cells; (b) a plurality of word lines each operative to activate the memory cells of each row in the read-out mode and the write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of the first data lines to form a data line pair coupled to the memory cells of each column, each of the second data lines being operative to propagate the complementary voltage level of the voltage level on the first data line, the voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of the data line pair so as to transfer the bit of data information thereto, wherein each of the read only memory cells comprises a series combination of two transistors capable of providing a conduction path between one of the first and second data lines and a source of voltage in the read-out mode, at least one of the two transistors being operative to block the conduction path in the write-in mode.
Inventors
- 👤 Shigeru Takayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:33
CPC Classifications
G; G11; G11C; G11C14/00; G11C11/00; G11C11/005
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
232 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and said write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto, wherein each of said read only memory cells comprises a series combination of two transistors capable of providing a conduction path between one of said first and second data lines and a source of voltage in said read-out mode, at least one of said two transistors being operative to block said conduction path in said write-in mode.
Claim 2
Dependent Claim
232 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and said write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto, wherein each of said read only memory cells comprises a series combination of two transistors capable of providing a conduction path between one of said first and second data lines and a source of voltage in said read-out mode, at least one of said two transistors being operative to block said conduction path in said write-in mode.
Claim 3
Dependent Claim
36 words
A semiconductor memory device as set forth in claim 1, in which said two transistors of each read only memory cell are formed by two field effect transistors of with respective channels of one conductivity type.
Claim 4
Dependent Claim
52 words
A semiconductor memory device as set forth in claim 2, in which one of said field effect transistors has a gate electrode coupled to one of said word lines and the other of said field effect transistors has a gate electrode coupled to the other of said first and second data lines.
Claim 5
Dependent Claim
22 words
A semiconductor memory device as set forth in claim 2, in which said two field effect transistors are of an n-channel type.
Claim 6
Dependent Claim
97 words
A semiconductor memory device as set forth in claim 1, in which said read-write buffer circuit is shifted from said readout mode to said write-in mode when a write control signal is supplied thereto and in which said two transistors are formed by two field effect transistors with respective channel of one conductivity type, wherein one of said field effect transistors has a gate electrode coupled to one of said word lines and the other of said field effect transistors has a gate electrode supplied with the inverse of said write control signal in said write-in mode.
Claim 7
Dependent Claim
277 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and said write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto and shifted from said read-out mode to said write-in mode in the presence of a write control signal of a positive voltage level, wherein each of said read only memory cells comprises a series combination of two field effect transistors capable of providing a conduction path between one of said first and second data lines and a source of ground voltage in said read-out mode, said two field effect transistors having respective gate electrodes one of which is coupled to one of said word lines and the other of which is coupled to the other of said first and second data lines.
Claim 8
Dependent Claim
277 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and said write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto and shifted from said read-out mode to said write-in mode in the presence of a write control signal of a positive voltage level, wherein each of said read only memory cells comprises a series combination of two field effect transistors capable of providing a conduction path between one of said first and second data lines and a source of ground voltage in said read-out mode, said two field effect transistors having respective gate electrodes one of which is coupled to one of said word lines and the other of which is coupled to the other of said first and second data lines.
Claim 9
Dependent Claim
278 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto and shifted from said read-out mode to said write-in mode in the presence of a write control signal of a positive voltage level, wherein each of said read only memory cells comprises a series combination of two field effect transistors capable of providing a conduction path between one of said first and second data lines and a source of ground voltage in said read-out mode, said two field effect transistors having respective gate electrodes one of which is coupled to one of said word lines and the other of which is supplied with the inverse of said write control signal in said write-in mode.
Claim 10
Dependent Claim
278 words
A semiconductor memory device fabricated on a semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of read only memory cells and random access memory cells arranged in rows and columns to form a memory cell array; (b) a plurality of word lines each operative to activate said memory cells of each row in said read-out mode and write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of said first data lines to form a data line pair coupled to said memory cells of each column, each of said second data lines being operative to propagate the complementary voltage level of said voltage level on the first data line, said voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of said data line pair so as to transfer said bit of data information thereto and shifted from said read-out mode to said write-in mode in the presence of a write control signal of a positive voltage level, wherein each of said read only memory cells comprises a series combination of two field effect transistors capable of providing a conduction path between one of said first and second data lines and a source of ground voltage in said read-out mode, said two field effect transistors having respective gate electrodes one of which is coupled to one of said word lines and the other of which is supplied with the inverse of said write control signal in said write-in mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |