Patent US4802122A successfully refreshed from Google Patents.
US4802122A
Expired / Lapsed
US
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Fast flush for a first-in first-out memory
Assignee: Advanced Micro Devices Inc
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Filing: 1987-04-28
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Granted: 1989-01-31
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Expires: 2007-04-28
Abstract
Abstract In a memory circuit including a write bit-line for writing data into a memory cell, and a read bit-line for reading data from the cell, a transistor is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.
Inventors
- 👤 Stuart T. Auvinen
- 👤 Barry A. Hoberman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:26
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G11; G11C; G11C7/00; G11C7/12; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
78 words
A circuit for reducing the fall-through delay of data in a memory cell comprising: a write bit-line connected with the memory cell for communicating data to the cell; a read bit-line connected with the memory cell for communicating data from the cell; and means selectively connecting the write bit-line with the read bit-line independent of the memory cell so that data carried by the write bit-line can be communicated to the read bit-line independent of the memory cell.
Claim 2
Dependent Claim
78 words
A circuit for reducing the fall-through delay of data in a memory cell comprising: a write bit-line connected with the memory cell for communicating data to the cell; a read bit-line connected with the memory cell for communicating data from the cell; and means selectively connecting the write bit-line with the read bit-line independent of the memory cell so that data carried by the write bit-line can be communicated to the read bit-line independent of the memory cell.
Claim 3
Dependent Claim
35 words
The circuit of claim 1 wherein the means for selectively connecting the write bit-line to the read bit-line independent of the memory cell comprise switch means operatively associated with the write bit-line and read bit-line.
Claim 4
Dependent Claim
54 words
The circuit of claim 2 wherein the switch means comprises an MOS transistor having a drain connected to the write bit-line, a source connected to the read bit-line, and a gate to which a signal may be applied for selectively providing communication through said MOS transistor between the write bit-line and the read bit-line.
Claim 5
Dependent Claim
20 words
The circuit of claim 3 and further comprising a sense amplifier connected with the read bit-line for receiving data therefrom.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |