Velocity error correcting circuit for time base error corrector

Claim 2

A time base corrector for correcting a time base error in a signal reproduced from a recording medium in a succession of interlaced fields each formed of a plurality of horizontal lines, each of said lines having a horizontal synchronization position which is shifted by 0.5 horizontal line between successive ones of said fields; said time base corrector comprising: a main memory for storing a signal reproduced from a recording medium with a time base error; read clock generator and phase modulator means for generating a read clock signal of variable phase for reading out said signal from said main memory; and a velocity error compensating circuit for generating first discrete signals representative of the velocity error of said reproduced signal at designated sample points of a current field and second discrete signals representative of the velocity error of said reproduced signal at sample points of a previous field respectively correspondign to said designated points and for interleaving said first and second discrete signals to produce a combined signal having a sampling frequency twice that of either of said first and second discrete signals; wherein said combined signal constitutes a nonlinear approximation of said time base error and said read clock generator and phase modulator means is responsive to said combined signal for controlling the readout of said reproduced signal from said main memory in such a manner as substantially to eliminate said time base error; and wherein said velocity error compensating circuit comprises a velocity error detector circuit for generating said first discrete signals, a field memory for delaying an output of said velocity error detector circuit by one field period to generate said second discrete signals, and switching means jointly responsive to said velocity error detector circuit and said field memory for generating said combined signal.

Claim 3

A time base corrector according to claim 1, wherein said read clock generator and phase modulator means comprises a self-timed read clock generator.

Claim 4

A time base corrector according to claim 1, wherein said read clock generator and phase modulator means is responsive to an external synchronizing signal.

Claim 5

A time base corrector according to claim 1; wherein said velocity error compensating circuit comprises a pair of memories for respectively generating said first discrete signals and said second discrete signals and a velocity error compensating signal output circuit jointly responsive to said pair of memories for generating said combined signal.

Claim 6

A time base corrector for correcting a time base error in a signal reproduced from a recording medium in a succession of fields, said time base corrector comprising: a main memory for storing a signal reproduced from a recording medium with a time base error; read clock generator and phase modulator means for generating a read clock signal of variable phases for reading out said signal from said main memory; and a velocity error compensating circuit for generating first discrete signals representative of the velocity error of said reproduced signal at designated sample points of a current field and second discrete signals representative of the velocity error of said reproduced signal at sample points of the previous field respectively corresponding to said designated points and for interleaving said first and second discrete signals to produce a combined signal having a sampling frequency greater than that of either of said first and second discrete signals; said combined signal constituting a nonlinear approximation of said time base error and said read clock generator and phase modulator means being responsive to said combined signal for controlling the readout of said reproduced signal from said main memory in such a manner as substantially to eliminate said time base error; wherein said velocity error compensating circuit comprises a pair of memories for respectively generating said first discrete signals and said second discrete signals and a velocity error compensating signal output circuit jointly responsive to said pair of memories for generating said combined signal; and wherein each field is divided into a plurality of periods H and said velocity error compensating signal output circuit comprises a 1/H multiplier responsive to said second discrete signals, a 1/H 2 multiplier and integrator jointly responsive to said first discrete signals and said second discrete signals, and a second integrator jointly responsive to said 1/H multiplier and said 1/H 2 multiplier and integrator to produce said combined signal.

Claim 7

A time base corrector for correcting a time base error in a signal reproduced from a recording medium in a succession of fields, said time base corrector comprising: a main memory for storing a signal reproduced from a recording medium with a time base error; read clock generator and phase modulator means for generating a read clock signal of variable phases for reading out said signal from said main memory; and a velocity error compensating circuit for generating first discrete signals representative of the velocity error of said reproduced signal at designated sample points of a current field and second discrete signals representative of the velocity error of said reproduced signal at sample points of the previous field respectively corresponding to said designated points and for interleaving said first and second discrete signals to produce a combined signal having a sampling frequency greater than that of either of said first and second discrete signals; said combined signal constituting a nonlinear approximation of said time base error and said read clock generator and phase modulator means being responsive to said combined signal for controlling the readout of said reproduced signal from said main memory in such a manner as substantially to eliminate said time base error; wherein said velocity error compensating circuit comprises a pair of memories for respectively generating said first discrete signals and said second discrete signals and a velocity error compensating signal output circuit jointly responsive to said pair of memories for generating said combined signal; and wherein each field is divided into a plurality of periods H and said velocity error compensating signal output circuit comprises a 1/H multiplier responsive to said second discrete signals, a 1/H 2 multiplier and integrator jointly responsive to said first discrete signals and said second discrete signals, and a second integrator jointly responsive to said 1/H multiplier and said 1/H 2 multiplier and integrator to produce said combined signal.