Patent US4801469A successfully refreshed from Google Patents.
US4801469A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for obtaining multiple sheet resistances for thin film hybrid microcircuit resistors
Assignee: United States Department of Energy
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Filing: 1986-08-07
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Granted: 1989-01-31
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Expires: 2006-08-07
Abstract
Abstract A standard thin film circuit containing Ta 2 N (100 ohms/square) resirs is fabricated by depositing on a dielectric substrate successive layers of Ta 2 N, Ti and Pd, with a gold layer to provide conductors. The addition of a few simple photoprocessing steps to the standeard TFN manufacturing process enables the formation of Ta 2 N+Ti (10 ohms/square) and Ta 2 N+Ti+Pd (1 ohm/square) resistors in the same otherwise standard thin film circuit structure.
Inventors
- 👤 David P. Norwood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:52
CPC Classifications
H; H01; H01C; H01C17/00; H01C17/003; H10; H10D; H10D86/00; H10D86/80; H10D86/85; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49099
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
242 words
A process of manufacturing on a surface of a substrate member a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by different resistivities, said process comprising the steps of: depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta 2 N) to a first thickness, said Ta 2 N layer having a high resistivity; depositing on said first layer of Ta 2 N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta 2 N+Ti having an intermediate resistivity; depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta 2 N+Ti+Pd having a low resistivity; masking a first portion of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths; masking a second portion of said third layer and said conductive paths, and subsequently removing the remainder of both said third layer and said second layer to expose said first layer thereunder said masked second portion defining said low resistivity resistor between two conductive paths; masking said low conductivity resistor, said conductive paths, and a third portion of said first layer exposed by the previous step, and subsequently removing the remainder of said exposed first layer, said masked third portion defining a resistivity resistor between two conductive paths in said TFN circuit.
Claim 2
Dependent Claim
242 words
A process of manufacturing on a surface of a substrate member a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by different resistivities, said process comprising the steps of: depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta 2 N) to a first thickness, said Ta 2 N layer having a high resistivity; depositing on said first layer of Ta 2 N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta 2 N+Ti having an intermediate resistivity; depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta 2 N+Ti+Pd having a low resistivity; masking a first portion of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths; masking a second portion of said third layer and said conductive paths, and subsequently removing the remainder of both said third layer and said second layer to expose said first layer thereunder said masked second portion defining said low resistivity resistor between two conductive paths; masking said low conductivity resistor, said conductive paths, and a third portion of said first layer exposed by the previous step, and subsequently removing the remainder of said exposed first layer, said masked third portion defining a resistivity resistor between two conductive paths in said TFN circuit.
Claim 3
Dependent Claim
34 words
A process according to claim 1, further comprising the step of: stabilizing said TFN resistors on said substrate by maintaining it in air at a temperature of approximately 300° C. for approximately two hours.
Claim 4
Dependent Claim
25 words
A process according to claim 1, wherein: said first thickness of said first layer comprising Ta 2 N is in the range 400 Å-1200 Å.
Claim 5
Dependent Claim
34 words
A process according to claim 3, wherein: said second thickness of said second layer comprising Ti is approximately 2000 Å; and said third thickness of said third layer comprising Pd is approximately 2000 Å.
Claim 6
Dependent Claim
22 words
A process according to claim 4, wherein: said pattern plating of gold provides a gold plating thickness in the range 3-6 microns.
Claim 7
Dependent Claim
291 words
A process of manufacturing on a surface of a substrate a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by having, respectively, low, intermediate and high resistivities, said process comprising the steps of: depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta 2 N) to a first thickness, said Ta 2 N layer having said high resistivity; depositing on said first layer of Ta 2 N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta 2 N+Ti having said intermediate resistivity; depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta 2 N+Ti+Pd having said low resistivity; masking an area of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths; masking said conductive paths and said third layer over a first portion of said area, and subsequently removing the remainder of said third layer to expose said second layer thereunder, said masked first portion defining said low resistivity resistor between two conductive paths; masking said low conductivity resistor, said conductive paths, and said exposed second layer over a second portion of said area, and subsequently removing the remainder of said exposed second layer to expose said first layer thereunder, said masked second portion defining said intermediate resistivity resistor between two conductive paths; and masking said intermediate and low resistivity resistors, said conductive paths, and said exposed first layer over a third portion of said area, and subsequently removing the remainder of said exposed first layer, said masked third portion defining said high resistivity resistor between two conductive paths.
Claim 8
Dependent Claim
291 words
A process of manufacturing on a surface of a substrate a thin film network (TFN) circuit including a plurality of resistors formed of materials characterized by having, respectively, low, intermediate and high resistivities, said process comprising the steps of: depositing on said surface of said substrate a first layer comprising tantalum nitride (Ta 2 N) to a first thickness, said Ta 2 N layer having said high resistivity; depositing on said first layer of Ta 2 N a second layer comprising titanium metal (Ti) to a second thickness, the combined layers of Ta 2 N+Ti having said intermediate resistivity; depositing on said second layer comprising Ti a third layer comprising palladium metal (Pd) to a third thickness, said combined layers of Ta 2 N+Ti+Pd having said low resistivity; masking an area of said third layer and subsequently plating the remainder of said third layer with gold to form a plurality of conductive paths; masking said conductive paths and said third layer over a first portion of said area, and subsequently removing the remainder of said third layer to expose said second layer thereunder, said masked first portion defining said low resistivity resistor between two conductive paths; masking said low conductivity resistor, said conductive paths, and said exposed second layer over a second portion of said area, and subsequently removing the remainder of said exposed second layer to expose said first layer thereunder, said masked second portion defining said intermediate resistivity resistor between two conductive paths; and masking said intermediate and low resistivity resistors, said conductive paths, and said exposed first layer over a third portion of said area, and subsequently removing the remainder of said exposed first layer, said masked third portion defining said high resistivity resistor between two conductive paths.
Claim 9
Dependent Claim
34 words
A process according to claim 6, further comprising the step of: stabilizing said TFN resistors on said substrate by maintaining it in air at a temperature of approximately 300° C. for approximately two hours.
Claim 10
Dependent Claim
25 words
A process according to claim 6, wherein: said first thickness of said first layer comprising Ta 2 N is in the range 400 Å-1200 Å.
Claim 11
Dependent Claim
34 words
A process according to claim 8, wherein: said second thickness of said second layer comprising Ti is approximately 2000 Å; and said third thickness of said third layer comprising Pd is approximately 2000 Å.
Claim 12
Dependent Claim
22 words
A process according to claim 9, wherein: said pattern plating of gold provides a gold plating thickness in the range 3-6 microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |