Telephone switching system frame sync generator

Claim 1

In a telephone switching system which includes a group of codecs, a separate analog line coupled to each codec, a bus output line common to all codecs in said group, and a separate timing input line coupled to each codec, the improvement of means for generating timing signals on said timing input lines, comprising: clock means for generating a high frequency clock signal; divider means coupled to said clock means, for generating a plurality of substantially square wave signals including a first binary signal of a first low frequency and a plurality of additional binary signals of progressive 2's multiples of said first frequency, all synchronized to the first signal; an integrated circuit which has a plurality of input lines that each represent a bit of predetermined significance and that each receive a different one of said binary signals, said integrated circuit also having a plurality of output lines that each carries a square wave only while the binary signals on its input lines define a predetermined number, whereby each of said output lines carries a square wave for a predetermined small minority of the time; each of said output lines is connected to a different one of said plurality of codecs, to control each codec to operate during a different short period of time to sample the analog signal on its analog line and deliver a burst of binary signals on said bus representing the analog signal sample; said system includes four of said integrated circuits; said divider means includes means for generating the inverse of said first low frequency signal and the inverse of a second signal whose frequency is twice said low frequency; each of said four integrated circuits receives a different combination of inverse and noninverse of said first low frequency signal and said second signal, with a first integrated circuit receiving said first and second signals, with a second integrated circuit receiving the noninverse of said first signal and the inverse of said second signal, with a third integrated circuit receiving the inverse of said first signal and the noninverse of said second signal, and with a fourth integrated circuit receiving the inverse of said first signal and the inverse of said second signal.