Patent US2393825A successfully refreshed from Google Patents.
Patent US4800489A successfully refreshed from Google Patents.
US4800489A
Expired / Lapsed
US
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Paged memory management unit capable of selectively supporting multiple address spaces
Assignee: NXP USA Inc
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Filing: 1988-05-19
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Granted: 1989-01-24
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Expires: 2008-05-19
Abstract
Abstract A paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables to obtain therefrom a page table pointer to a selected one of the page tables and then combining a second portion of the logical address and the page table pointer to access the selected page table to obtain therefrom the physical address. If desired, an address space selector may be considered as an extension of the logical address. If so, the PMMU may be selectively enabled to initially combine the first table pointer and the address space selector to access a second one of the pointer tables to obtain therefrom a second table pointer and then combine the first portion of the logical address and the second table pointer to access the first one of the pointer tables to obtain therefrom the page table pointer. In the preferred form, the first table pointer is a selected one of several root pointers.
Inventors
- 👤 William C. Moyer
- 👤 Michael W. Cruess
- 👤 William M. Keshlear
- 👤 John Zolnowsky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/14; G06F12/1416; G06F12/145; G06F12/0802; G06F12/0877; G06F12/0882; G06F12/1027; G06F12/1045
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
134 words
In a paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining an address space selector portion of said logical address and a root pointer to access a selected one of said pointer tables to obtain therefrom a page table pointer to a selected one of said page tables and then combining a second portion of said logical address and said page table pointer to access said selected page table to obtain therefrom said physical address, the improvement wherein said PMMU is selectively enabled to combine said root pointer and said second portion of said logical address to directly access said page table to obtain therefrom said physical address.
Claim 2
Dependent Claim
134 words
In a paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining an address space selector portion of said logical address and a root pointer to access a selected one of said pointer tables to obtain therefrom a page table pointer to a selected one of said page tables and then combining a second portion of said logical address and said page table pointer to access said selected page table to obtain therefrom said physical address, the improvement wherein said PMMU is selectively enabled to combine said root pointer and said second portion of said logical address to directly access said page table to obtain therefrom said physical address.
Claim 3
Dependent Claim
18 words
In the PMMU of claim 1 wherein said root pointer is selected from a plurality of root pointers.
Claim 4
Dependent Claim
134 words
In a paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of said logical address and a first table pointer to access a selected one of said pointer tables to obtain therefrom a page table pointer to a selected one of said page tables and then combining a second portion of said logical address and said page table pointer to access said selected page table to obtain therefrom said physical address, the improvement wherein said PMMU is selectively enabled to combine said first table pointer and said second portion of said logical address to directly access said page table to obtain therefrom said physical address.
Claim 5
Dependent Claim
134 words
In a paged memory management unit (PMMU) adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address into a corresponding physical address by first combining a first portion of said logical address and a first table pointer to access a selected one of said pointer tables to obtain therefrom a page table pointer to a selected one of said page tables and then combining a second portion of said logical address and said page table pointer to access said selected page table to obtain therefrom said physical address, the improvement wherein said PMMU is selectively enabled to combine said first table pointer and said second portion of said logical address to directly access said page table to obtain therefrom said physical address.
Claim 6
Dependent Claim
19 words
In the PMMU of claim 3 wherein said first table pointer is selected from a plurality of root pointers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-24 | 1992-07-25 | 1993-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-24 | 1996-07-25 | 1997-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-24 | 2000-07-25 | 2001-01-24 | $7700.00 | Window Closed / Lapsed |