Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
170 words
A circuit arrangement for a television receiver comprising a television signal decoder, said television signal decoder deriving from a television signal applied to its input a luminance signal supplied by a luminance signal output via a low-pass filter arrangement for suppressing a chrominance signal, and comprising a video test decoder, producing signals from video text data from which driving signals for a picture display device can be derived, characterized in that the input of the video text decoder is coupled to the luminance signal output, in that the low-pass filter arrangement has a first attenuation characteristic to suppress the chrominance signal and a second attenuation characteristic to allow all video text data to pass in that the attenuation characteristic of the low-pass filter arrangement is changed over by means of a change-over signal derived from the television signal by a change-over device so that the second attenuation characteristic of the low-pass filter arrangement is switched on at least during the periods of time in which the video text data occur.
Claim 2
Dependent Claim
170 words
A circuit arrangement for a television receiver comprising a television signal decoder, said television signal decoder deriving from a television signal applied to its input a luminance signal supplied by a luminance signal output via a low-pass filter arrangement for suppressing a chrominance signal, and comprising a video test decoder, producing signals from video text data from which driving signals for a picture display device can be derived, characterized in that the input of the video text decoder is coupled to the luminance signal output, in that the low-pass filter arrangement has a first attenuation characteristic to suppress the chrominance signal and a second attenuation characteristic to allow all video text data to pass in that the attenuation characteristic of the low-pass filter arrangement is changed over by means of a change-over signal derived from the television signal by a change-over device so that the second attenuation characteristic of the low-pass filter arrangement is switched on at least during the periods of time in which the video text data occur.
Claim 3
Dependent Claim
21 words
A circuit arrangement as claimed in claim 1, characterized in that the change-over device derives the change-over signal from synchronizing pulses.
Claim 4
Dependent Claim
22 words
A circuit arrangement as claimed in claim 2, characterized in that the change-over device derives the change-over signal from vertical synchronizing pulses.
Claim 5
Dependent Claim
37 words
A circuit arrangement as claimed in claim 1, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 6
Dependent Claim
63 words
A circuit arrangement as claimed in claim 1, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 7
Dependent Claim
37 words
A circuit arrangement as claimed in claim 2, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 8
Dependent Claim
37 words
A circuit arrangement as claimed in claim 3, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 9
Dependent Claim
63 words
A circuit arrangement as claimed in claim 2, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 10
Dependent Claim
63 words
A circuit arrangement as claimed in claim 3, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 11
Dependent Claim
63 words
A circuit arrangement as claimed in claim 4, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 12
Dependent Claim
63 words
A circuit arrangement as claimed in claim 6, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 13
Dependent Claim
63 words
A circuit arrangement as claimed in claim 7, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.