US4800428A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for a television receiver comprising a video text decoder
Assignee: JAMBON GROUP INC.
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Filing: 1987-05-11
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Granted: 1989-01-24
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Expires: 2007-05-11
Abstract
Abstract A circuit arrangement for a television receiver including a video text decoder (30), producing signals from the video text data from which control signals for a picture display device can be derived. The circuit arrangement further including a television signal decoder (1), deriving from the television signal via a low-pass filter arrangement (15) the luminance signal which can be taken from the luminance signal output (18). The low-pass filter arrangement (15) has a first attenuation characteristic for suppressing the chrominance signal and a second attenuation characteristic for allowing all video text data to pass. The second attenuation characteristic of the low-pass filter arrangement (15) is used during the period of time in which the video text data occur. The input of the video text decoder (30) is coupled to the luminance signal output (18) of the television signal decoder (1).
Inventors
- 👤 Martin H. Johanndeiter
- 👤 Detlef W. K. Oldach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:08
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/641; H04N7/00; H04N7/08; H04N7/087; H04N7/088; H04N7/0882
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
170 words
A circuit arrangement for a television receiver comprising a television signal decoder, said television signal decoder deriving from a television signal applied to its input a luminance signal supplied by a luminance signal output via a low-pass filter arrangement for suppressing a chrominance signal, and comprising a video test decoder, producing signals from video text data from which driving signals for a picture display device can be derived, characterized in that the input of the video text decoder is coupled to the luminance signal output, in that the low-pass filter arrangement has a first attenuation characteristic to suppress the chrominance signal and a second attenuation characteristic to allow all video text data to pass in that the attenuation characteristic of the low-pass filter arrangement is changed over by means of a change-over signal derived from the television signal by a change-over device so that the second attenuation characteristic of the low-pass filter arrangement is switched on at least during the periods of time in which the video text data occur.
Claim 2
Dependent Claim
170 words
A circuit arrangement for a television receiver comprising a television signal decoder, said television signal decoder deriving from a television signal applied to its input a luminance signal supplied by a luminance signal output via a low-pass filter arrangement for suppressing a chrominance signal, and comprising a video test decoder, producing signals from video text data from which driving signals for a picture display device can be derived, characterized in that the input of the video text decoder is coupled to the luminance signal output, in that the low-pass filter arrangement has a first attenuation characteristic to suppress the chrominance signal and a second attenuation characteristic to allow all video text data to pass in that the attenuation characteristic of the low-pass filter arrangement is changed over by means of a change-over signal derived from the television signal by a change-over device so that the second attenuation characteristic of the low-pass filter arrangement is switched on at least during the periods of time in which the video text data occur.
Claim 3
Dependent Claim
21 words
A circuit arrangement as claimed in claim 1, characterized in that the change-over device derives the change-over signal from synchronizing pulses.
Claim 4
Dependent Claim
22 words
A circuit arrangement as claimed in claim 2, characterized in that the change-over device derives the change-over signal from vertical synchronizing pulses.
Claim 5
Dependent Claim
37 words
A circuit arrangement as claimed in claim 1, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 6
Dependent Claim
63 words
A circuit arrangement as claimed in claim 1, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 7
Dependent Claim
37 words
A circuit arrangement as claimed in claim 2, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 8
Dependent Claim
37 words
A circuit arrangement as claimed in claim 3, characterized in that a combining stage receives the output signals from the television signal decoder and the video text decoder to produce control signals for the picture display device.
Claim 9
Dependent Claim
63 words
A circuit arrangement as claimed in claim 2, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 10
Dependent Claim
63 words
A circuit arrangement as claimed in claim 3, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 11
Dependent Claim
63 words
A circuit arrangement as claimed in claim 4, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 12
Dependent Claim
63 words
A circuit arrangement as claimed in claim 6, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
Claim 13
Dependent Claim
63 words
A circuit arrangement as claimed in claim 7, characterized in that the television signal decoder is designed as a digital processor, processing a television signal converted by means of an analog-to-digital converter which signal is available as a sequence of amplitude-discrete sampling values having a clock signal determined sampling rate and continuously supplying from its outputs a signal converted by a digital-to-analog converter.
References Cited (Backward Citations)
US4393404A
Cited
US4388639A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-24 | 1992-07-25 | 1993-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-24 | 1996-07-25 | 1997-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-24 | 2000-07-25 | 2001-01-24 | $7700.00 | Window Closed / Lapsed |