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US4797807A
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Multiple channel fast orthogonalization network
Assignee: United States, AS REPRESENTED BY THRE SECRETARY OF NAVY
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Filing: 1985-08-02
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Granted: 1989-01-10
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Expires: 2005-08-02
Abstract
Abstract A method for orthogonalizing inputs with respect to each other. The method comprises the steps of: generating a root structure of N inputs having input order 1 to N, where 2m-1<N</=2m and m is an integer >/=1; inverting the order of the root structure to generate an inverted root structure having input order N to 1; partially orthogonalizing the root structure and the inverted root structure in associated respective decorrelation circuits to remove inputs common to their first 2m-I inputs where I=1; splitting off two substructures from the root structure, where the first substructure has input order 1 to 2m-I and the second substructure has input order 2m-I to 1, where I=1; splitting off two substructures from the inverted root structure, where the first substructure has input order 2m to 2m-I and the second substructure has input order 2m-I to 2m, where I=1; partially orthogonalizing each of the substructures in associated respective decorrelation circuits to remove inputs common to their first 2m-I inputs, where I=2; and repeating the splitting off steps and the subsequent partially orthogonalizing step until only one input remains, where for each repetition the substructures that are split-off are treated as new root structure and new inverted root structure, and the value identified for I in each step is increased by 1.
Inventors
- 👤 Karl Gerlach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:57
CPC Classifications
H; H03; H03H; H03H21/00; H03H21/0012
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
277 words
A fast orthogonalization network for orthogonalizing N inputs with respect to each other, where N=2 m and m=2, said network comprising: first means responsive to a root structure of the N inputs in input order 1 to N for partially orthogonalizing said root structure inputs with respect to their common inputs so that the 1 to 2 m-1 inputs are decorrelated with respect to inputs 2 m-1 to 2 m ; second means responsive to an inverted root structure of the N inputs in input order N to 1 for partially orthogonalizing said inverted root structure inputs with respect to their common inputs so the 2 m to 2 m-1 +1 inputs are decorrelated with respect to inputs 1 to 2 m-1 ; third means responsive to a first root substructure of inputs 1 to 2 m-1 from said first means for orthogonalizing said first root substructure so input 1 is decorrelated with respect to input 2 m-1 ; fourth means responsive to a second root substructure of inputs 1 to 2 m-1 from said first means for orthogonalizing said second root substructure so input 2 m-1 is decorrelated with respect to input 1; fifth means responsive to a first inverted root substructure of inputs 2 m to 2 m-1 +1 from said second means for orthogonalizing said first inverted root substructure so input 2 m is decorrelated with respect to 2 m-1 +1; and sixth means responsive to a second inverted root substructure of inputs 2 m to 2 m-1 +1 from said second means for orthogonalizing said second inverted root substructure so input 2 m-1 +1 is decorrelated with respect to input 2 m .
Claim 2
Dependent Claim
277 words
A fast orthogonalization network for orthogonalizing N inputs with respect to each other, where N=2 m and m=2, said network comprising: first means responsive to a root structure of the N inputs in input order 1 to N for partially orthogonalizing said root structure inputs with respect to their common inputs so that the 1 to 2 m-1 inputs are decorrelated with respect to inputs 2 m-1 to 2 m ; second means responsive to an inverted root structure of the N inputs in input order N to 1 for partially orthogonalizing said inverted root structure inputs with respect to their common inputs so the 2 m to 2 m-1 +1 inputs are decorrelated with respect to inputs 1 to 2 m-1 ; third means responsive to a first root substructure of inputs 1 to 2 m-1 from said first means for orthogonalizing said first root substructure so input 1 is decorrelated with respect to input 2 m-1 ; fourth means responsive to a second root substructure of inputs 1 to 2 m-1 from said first means for orthogonalizing said second root substructure so input 2 m-1 is decorrelated with respect to input 1; fifth means responsive to a first inverted root substructure of inputs 2 m to 2 m-1 +1 from said second means for orthogonalizing said first inverted root substructure so input 2 m is decorrelated with respect to 2 m-1 +1; and sixth means responsive to a second inverted root substructure of inputs 2 m to 2 m-1 +1 from said second means for orthogonalizing said second inverted root substructure so input 2 m-1 +1 is decorrelated with respect to input 2 m .
Claim 3
Dependent Claim
172 words
The fast orthogonalization network of claim 1 wherein: each of said first and second means is comprised of 2 m-1 levels of decorrelation processors (DP's), with the level receiving said root structure inputs and said inverted root structure inputs having 2 m -1 DP's, each DP being connected to a unique input and the highest order input, all subsequent levels of DP's in each of said first and second means having 1 DP less than the preceding level; each level of DP's having outputs, the number of outputs equal to the number of DP's in that level, each DP of each subsequent level of DP's after the level receiving said root structure inputs and said inverted root structure inputs receiving a unique input from the preceding level of DP's, along with the highest order input at each level if said highest order input is a root of said root structure, or the lowest order input at each level if said lowest order input is an inverted root of said inverted root substructure.
Claim 4
Independent Claim
333 words
A method for orthogonalizing N data inputs to a fast orthogonalization network with respect to each other, where 2 m-1 <N≦2 m and m is an integer ≧1, said method comprising the steps of: a. arranging the N data inputs to the fast orthogonalization network into a first group having a data input order of 1 to N; b. arranging the N data inputs to the fast orthogonalization network into a second group having a data input order of N to 1; c. partially orthogonalizing in a first decorrelation circuit of the fast orthogonalization network the N data inputs in said first group to remove data inputs common to the first 2 m-1 inputs in said first group, where I=1; d. partially orthogonalizing in a second decorrelation circuit of the fast orthogonalization network the N data inputs in said second group to remove data inputs common to the first 2 m-I data inputs in said second group, where I=1; e. splitting off the partially orthogonalized N data inputs in said first group into a first subgroup having data input order 1 to 2 m-I and a second subgroup having data input order 2 m-I to 1, where I=1; f. splitting off the partially orthogonalized N data inputs in said second group into a third subgroup having data input order 2 m to 2 m-I and a fourth subgroup having data input order 2 m-I to 2 m , where I=1; g. partially orthogonalizing the first through fourth subgroups in associated respective third, fourth, fifth and sixth decorrelation circuits of the fast orthogonalization network to remove data inputs common to their first 2 m-I data inputs, where I equals 2; and h. repeating steps e, f and g until only one data input remains, where for each repetition the subgroups that are split off are treated as a new first group and a new second group, and the value identified for I in each of steps e, f and g is increased by 1.
Claim 5
Independent Claim
333 words
A method for orthogonalizing N data inputs to a fast orthogonalization network with respect to each other, where 2 m-1 <N≦2 m and m is an integer ≧1, said method comprising the steps of: a. arranging the N data inputs to the fast orthogonalization network into a first group having a data input order of 1 to N; b. arranging the N data inputs to the fast orthogonalization network into a second group having a data input order of N to 1; c. partially orthogonalizing in a first decorrelation circuit of the fast orthogonalization network the N data inputs in said first group to remove data inputs common to the first 2 m-1 inputs in said first group, where I=1; d. partially orthogonalizing in a second decorrelation circuit of the fast orthogonalization network the N data inputs in said second group to remove data inputs common to the first 2 m-I data inputs in said second group, where I=1; e. splitting off the partially orthogonalized N data inputs in said first group into a first subgroup having data input order 1 to 2 m-I and a second subgroup having data input order 2 m-I to 1, where I=1; f. splitting off the partially orthogonalized N data inputs in said second group into a third subgroup having data input order 2 m to 2 m-I and a fourth subgroup having data input order 2 m-I to 2 m , where I=1; g. partially orthogonalizing the first through fourth subgroups in associated respective third, fourth, fifth and sixth decorrelation circuits of the fast orthogonalization network to remove data inputs common to their first 2 m-I data inputs, where I equals 2; and h. repeating steps e, f and g until only one data input remains, where for each repetition the subgroups that are split off are treated as a new first group and a new second group, and the value identified for I in each of steps e, f and g is increased by 1.
Claim 6
Dependent Claim
175 words
A fast orthogonalization network for orthogonalizing inputs 1, 2, 3 and 4 with respect to each other, said network comprising: first means selectively responsive to the inputs 1, 2, 3 and 4 for partially decorrelating the inputs 1 and 2 with respect to the inputs 3 and 4; second means selectively responsive to the inputs 1, 2, 3 and 4 for partially decorrelating the inputs 3 and 4 with respect to the inputs 1 and 2; third means responsive to the partially decorrelated inputs 1 and 2 from said first means for decorrelating input 1 with respect to input 2; fourth means responsive to the partially decorrelated inputs 1 and 2 from said first means for decorrelating input 2 with respect to input 1; fifth means responsive to the partially decorrelated inputs 3 and 4 from said second means for decorrelating input 3 with respect to input 4; and sixth means responsive to the partially decorrelated inputs 3 and 4 from said second means for decorrelating the input 4 with respect to the input 3.
Claim 7
Dependent Claim
175 words
A fast orthogonalization network for orthogonalizing inputs 1, 2, 3 and 4 with respect to each other, said network comprising: first means selectively responsive to the inputs 1, 2, 3 and 4 for partially decorrelating the inputs 1 and 2 with respect to the inputs 3 and 4; second means selectively responsive to the inputs 1, 2, 3 and 4 for partially decorrelating the inputs 3 and 4 with respect to the inputs 1 and 2; third means responsive to the partially decorrelated inputs 1 and 2 from said first means for decorrelating input 1 with respect to input 2; fourth means responsive to the partially decorrelated inputs 1 and 2 from said first means for decorrelating input 2 with respect to input 1; fifth means responsive to the partially decorrelated inputs 3 and 4 from said second means for decorrelating input 3 with respect to input 4; and sixth means responsive to the partially decorrelated inputs 3 and 4 from said second means for decorrelating the input 4 with respect to the input 3.
Claim 8
Dependent Claim
413 words
A fast orthogonalization network for orthogonalizing inputs 1, 2, 3, 4, 5, 6, 7 and 8 with respect to each other, said network comprising: first means selectively responsive to the inputs 1 through 8 for partially decorrelating the inputs 1 through 4 with respect to the inputs 5 through 8; second means selectively responsive to the inputs 1 through 8 for partially decorrelating the inputs 5 through 8 with respect to the inputs 1 through 4; third means selectively responsive to the partially decorrelated inputs 1 through 4 from said first means for partially decorrelating the partially decorrelated inputs 1 and 2 with respect to the partially decorrelated inputs 3 and 4; fourth means selectively responsive to the partially decorrelated inputs 1 through 4 from said first means for partially decorrelating the partially decorrelated inputs 3 and 4 with respect to the partially decorrelated inputs 1 and 2; fifth means selectively responsive to the partially decorrelated inputs 5 through 8 from said second means for partially decorrelating the partially decorrelated inputs 5 and 6 with respect to the partially decorrelated inputs 7 and 8; sixth means selectively responsive to the partially decorrelated inputs 5 through 8 from said second means for partially decorrelating the partially decorrelated inputs 7 and 8 with respect to the partially decorrelated inputs 5 and 6; seventh means responsive to the partially decorrelated inputs 1 and 2 from said third means for decorrelating input 1 with respect to input 2; eighth means responsive to the partially decorrelated inputs 1 and 2 from said third means for decorrelating input 2 with respect to input 1; ninth means responsive to the partially decorrelated inputs 3 and 4 from said fourth means for decorrelating input 3 with respect to input 4; tenth means responsive to the partially decorrelated inputs 3 and 4 from said fourth means for decorrelating input 4 with respect to input 3; eleventh means responsive to the partially decorrelated inputs 5 and 65 from said fifth means for decorrelating input 5 with respect to input 6; twelfth means responsive to the partially decorrelated inputs 5 and 6 from said fifth means for decorrelating input 6 with respect to input 5; thirteenth means responsive to the partially decorrelated inputs 7 and 8 from said sixth means for decorrelating input 7 with respect to input 8; and fourteenth means responsive to the partially decorrelated inputs 7 and 8 from said sixth means for decorrelating input 8 with respect to input 7.
Claim 9
Dependent Claim
413 words
A fast orthogonalization network for orthogonalizing inputs 1, 2, 3, 4, 5, 6, 7 and 8 with respect to each other, said network comprising: first means selectively responsive to the inputs 1 through 8 for partially decorrelating the inputs 1 through 4 with respect to the inputs 5 through 8; second means selectively responsive to the inputs 1 through 8 for partially decorrelating the inputs 5 through 8 with respect to the inputs 1 through 4; third means selectively responsive to the partially decorrelated inputs 1 through 4 from said first means for partially decorrelating the partially decorrelated inputs 1 and 2 with respect to the partially decorrelated inputs 3 and 4; fourth means selectively responsive to the partially decorrelated inputs 1 through 4 from said first means for partially decorrelating the partially decorrelated inputs 3 and 4 with respect to the partially decorrelated inputs 1 and 2; fifth means selectively responsive to the partially decorrelated inputs 5 through 8 from said second means for partially decorrelating the partially decorrelated inputs 5 and 6 with respect to the partially decorrelated inputs 7 and 8; sixth means selectively responsive to the partially decorrelated inputs 5 through 8 from said second means for partially decorrelating the partially decorrelated inputs 7 and 8 with respect to the partially decorrelated inputs 5 and 6; seventh means responsive to the partially decorrelated inputs 1 and 2 from said third means for decorrelating input 1 with respect to input 2; eighth means responsive to the partially decorrelated inputs 1 and 2 from said third means for decorrelating input 2 with respect to input 1; ninth means responsive to the partially decorrelated inputs 3 and 4 from said fourth means for decorrelating input 3 with respect to input 4; tenth means responsive to the partially decorrelated inputs 3 and 4 from said fourth means for decorrelating input 4 with respect to input 3; eleventh means responsive to the partially decorrelated inputs 5 and 65 from said fifth means for decorrelating input 5 with respect to input 6; twelfth means responsive to the partially decorrelated inputs 5 and 6 from said fifth means for decorrelating input 6 with respect to input 5; thirteenth means responsive to the partially decorrelated inputs 7 and 8 from said sixth means for decorrelating input 7 with respect to input 8; and fourteenth means responsive to the partially decorrelated inputs 7 and 8 from said sixth means for decorrelating input 8 with respect to input 7.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-01-10 | 1992-07-11 | 1993-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-10 | 1996-07-11 | 1997-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-10 | 2000-07-11 | 2001-01-10 | $7700.00 | Window Closed / Lapsed |