US4796218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arithmetic circuit capable of executing floating point operation and fixed point operation
Assignee: NEC Electronics Corp
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Filing: 1987-02-18
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Granted: 1989-01-03
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Expires: 2007-02-18
Abstract
Abstract An arithmetic circuit comprises a pair of input registers for holding a pair of given numbers, and a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given numbers. This adjsutment circuit is capable of outputting at least a pair of radix point aligned fractions and one exponent derived from the radix point alignment. An arithmetic operation circuit receives the pair of the radix point aligned fractions, and outputs the result of a given arithmetic operation of the received fractions and generates an overflow signal when an overflow is generated in the arithmetic operation of the received fractions. An exponent correction circuit receives the exponent from the adjustment circuit, and is responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent. A fraction correction circuit receives the output of the arithmetic operation circuit so as to correct the received data. There is provided a first selector receiving the output of the exponent correction circuit and responsive to a given control signal so as to selectively output the output of the exponent correction circuit or a predetermined value. Further, a second selector is provided to receive the outputs of the arithmetic operation circuit and the fraction correction circuit so as to selectively output one of the two received fractions in response to the control signal.
Inventors
- 👤 Hideo Tanaka
- 👤 Takao Nishitani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/499; G06F7/49936
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
An arithmetic circuit capable of selectively executing both a floating-point operation and a fixed-point operation, comprising; a pair of input registers for holding a given pair of numbers in a floating-point format or in a fixed-point format, a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given pair of numbers, the adjustment circuit being capable of outputting a pair of radix point aligned fractions and one exponent derived from the radix point alignment, an arithmetic operation circuit receiving the pair of the radix point aligned fractions so as to output the result of a given arithmetic operation of the received fractions and to generate an overflow signal when an overflow is generated in the arithmetic operation of the received fractions, an exponent correction circuit receiving the exponent from the adjustment circuit and responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent, a fraction correction circuit receiving the output of the arithmetic operation circuit so as to correct the received data, a first selector receiving the output of the exponent correction circuit and responsive to a mode selection signal so as to selectively output the output of the exponent correction circuit or a predetermined value, and a second selector receiving the outputs of the arithmetic operation circuit and the fraction correction circuit and responsive to the mode selection signal so as to selectively output one of the two received fractions.
Claim 2
Dependent Claim
246 words
An arithmetic circuit capable of selectively executing both a floating-point operation and a fixed-point operation, comprising; a pair of input registers for holding a given pair of numbers in a floating-point format or in a fixed-point format, a radix point adjustment circuit coupled to the input registers for aligning the radix points of the given pair of numbers, the adjustment circuit being capable of outputting a pair of radix point aligned fractions and one exponent derived from the radix point alignment, an arithmetic operation circuit receiving the pair of the radix point aligned fractions so as to output the result of a given arithmetic operation of the received fractions and to generate an overflow signal when an overflow is generated in the arithmetic operation of the received fractions, an exponent correction circuit receiving the exponent from the adjustment circuit and responsive to the overflow signal from the arithmetic operation circuit so as to selectively correct the received exponent, a fraction correction circuit receiving the output of the arithmetic operation circuit so as to correct the received data, a first selector receiving the output of the exponent correction circuit and responsive to a mode selection signal so as to selectively output the output of the exponent correction circuit or a predetermined value, and a second selector receiving the outputs of the arithmetic operation circuit and the fraction correction circuit and responsive to the mode selection signal so as to selectively output one of the two received fractions.
Claim 3
Dependent Claim
28 words
A circuit as claimed in claim 1 further including a decoder connected to receive at least one bit of an instruction register for generating the mode selection signal.
Claim 4
Dependent Claim
106 words
A circuit as claimed in claim 1 further including a control circuit receiving the mode selection signal and the overflow signal for controlling the second selector, so that the second selector outputs the output of the fraction correction circuit when the mode selection signal is indicative of the floating-point operation and when the overflow signal indicates occurrence of an overflow, and the second selector outputs the output of the arithmetic operation circuit when the mode selection signal is indicative of the floating-point operation but the overflow signal does not indicate occurrence of an overflow or when the mode selection signal is indicative of the fixed-point operation.
Claim 5
Dependent Claim
100 words
A circuit claimed in claim 3 wherein the first selector includes an array of unitary transfer circuits, each of which includes a pair of first and second transfer gates coupled at one ends thereof to a corresponding bit of an exponent portion of the output register, the first transfer gate of each pair being coupled at the other end thereof to a corresponding bit output of the exponent correction circuit, the second transfer gate of each pair being coupled to receive a logic level "0" at the other end thereof, each pair of the transfer gates being alternatively turned on.
Claim 6
Dependent Claim
125 words
A circuit claimed in claim 1 wherein the fraction correction circuit and the second selector are composed of an array of unitary transfer circuits, each of which includes a pair of first and second transfer gates coupled at one end thereof to a corresponding bit of a fraction portion of the output register, the first transfer gate of each pair being coupled at the other end thereof to a corresponding bit output of the fraction arithmetic operation circuit, the second transfer gate of each pair being coupled at the other end thereof to a bit output of the fraction arithmetic operation circuit leftwardly adjacent to the corresponding bit output of the fraction arithmetic operation circuit, each pair of the transfer gates being alternatively turned on.
Claim 7
Dependent Claim
142 words
A circuit as claimed in claim 5 further including a decoder for generating a pair of first and second mode selection signals in opposite phase to each other and a control circuit receiving the overflow signal and the first and second mode selection signals for controlling each pair of first and second transfer gates, so that the first transfer gate of each pair is turned off and the second transfer gate is turned on when the mode selection signal is indicative of a floating point operation and when the overflow signal indicates occurrence of an overflow, and the first and second transfer gates are on and off, respectively, when the mode selection signal is indicative of the floating-point operation but the overflow signal does not indicate occurrence of an overflow or when the mode selection signal is indicative of the fixed-point operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-03 | 1992-07-04 | 1993-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-03 | 1996-07-04 | 1997-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-03 | 2000-07-04 | 2001-01-03 | $7700.00 | Window Closed / Lapsed |