Multi-marker, multi-destination timing signal generator

Claim 1

An apparatus for generating a sequence of timing signals comprising: counting means, connected to a source of clock pulses, for counting the pulses and for providing a pulse count value which is a sum of clock pulses counted; storing means for storing a plurality of pulse count values each pulse count value corresponding to a sum of clock pulses to be counted by the counting means; selecting means, connected to the storing means, for selecting a pulse count value in the storing means; determining means, connected to the counting means, to the storing means, and to the selecting means, for supplying a match signal when the counting means has counted a number of pulses which is the same as the selected pulse count value; generating means, connected to the determining means, for generating a first timing signal in response to the match signal; and wherein the selecting means selects a different pulse count value in the storing means in response to the match signal.

Claim 2

An apparatus for generating a sequence of timing signals comprising: counting means, connected to a source of clock pulses, for counting the pulses and for providing a pulse count value which is a sum of clock pulses counted; storing means for storing a plurality of pulse count values each pulse count value corresponding to a sum of clock pulses to be counted by the counting means; selecting means, connected to the storing means, for selecting a pulse count value in the storing means; determining means, connected to the counting means, to the storing means, and to the selecting means, for supplying a match signal when the counting means has counted a number of pulses which is the same as the selected pulse count value; generating means, connected to the determining means, for generating a first timing signal in response to the match signal; and wherein the selecting means selects a different pulse count value in the storing means in response to the match signal.

Claim 12

An apparatus for communicating a signal to a plurality of output elements comprising: a plurality of enabling elements, each connected to an associated output element and to a common signal source for receiving the signal therefrom; an addressable binary memory, connected to the enabling elements, for storing a plurality of enabling signals at addresses therein and for communicating an enabling signal to a selected enabling element, wherein the enabling element includes means for communicating the common signal from the signal source to an output element in response to the enabling signal and for so long as the enabling signal is being received by the enabling element; and addressing means, connected to the memory, for addressing the enabling signals stored in the memory to be communicated to the enabling elements.

Claim 13

An apparatus for communicating a signal to a plurality of output elements comprising: a plurality of enabling elements, each connected to an associated output element and to a common signal source for receiving the signal therefrom; an addressable binary memory, connected to the enabling elements, for storing a plurality of enabling signals at addresses therein and for communicating an enabling signal to a selected enabling element, wherein the enabling element includes means for communicating the common signal from the signal source to an output element in response to the enabling signal and for so long as the enabling signal is being received by the enabling element; and addressing means, connected to the memory, for addressing the enabling signals stored in the memory to be communicated to the enabling elements.

Claim 15

An apparatus for communicating a signal to a plurality of output elements comprising: counting means, connected to a source of clock pulses, for counting the pulses; storing means for storing a pulse count value; determining means, connected to the counting means and to the storing means, for supplying a match signal when the counting means has counted a number of pulses which is the same as the pulse count value; generating means, connected to the determining means, for generating the signal in response to the match signal; a plurality of enabling elements, each connected to the generating means and to an associated output element; an addressable binary memory, connected to the enabling elements, for storing a plurality of enabling signals at addresses therein and for communicating an enabling signal to an associated enabling element so that the enabling element communicates the timing signal from the generating means to an output element; and addressing means, connected to the memory, for addressing the enabling signals stored in the memory to be communicated to the enabling elements.

Claim 16

An apparatus for communicating a signal to a plurality of output elements comprising: counting means, connected to a source of clock pulses, for counting the pulses; storing means for storing a pulse count value; determining means, connected to the counting means and to the storing means, for supplying a match signal when the counting means has counted a number of pulses which is the same as the pulse count value; generating means, connected to the determining means, for generating the signal in response to the match signal; a plurality of enabling elements, each connected to the generating means and to an associated output element; an addressable binary memory, connected to the enabling elements, for storing a plurality of enabling signals at addresses therein and for communicating an enabling signal to an associated enabling element so that the enabling element communicates the timing signal from the generating means to an output element; and addressing means, connected to the memory, for addressing the enabling signals stored in the memory to be communicated to the enabling elements.

Claim 18

A method for generating a sequence of timing signals comprising the steps of: A. storing a plurality of unique pulse count values in addresses of a memory; B. counting pulses from a source of clock pulses to provide a sum of pulses counted; C. comparing a pulse count value stored at a memory address to the sum of counted clock pulses; D. indicating when the pulse count value stored at the memory address equals the sum of counted clock pulses; E. setting the memory to an address having a higher pulse count value in response to the indication that the pulse count value stored at the memory address is equal to the sum of counted clock pulses; and F. repeating steps C-E for each pulse count value in the memory.

Claim 19

A method for generating a sequence of timing signals comprising the steps of: A. storing a plurality of unique pulse count values in addresses of a memory; B. counting pulses from a source of clock pulses to provide a sum of pulses counted; C. comparing a pulse count value stored at a memory address to the sum of counted clock pulses; D. indicating when the pulse count value stored at the memory address equals the sum of counted clock pulses; E. setting the memory to an address having a higher pulse count value in response to the indication that the pulse count value stored at the memory address is equal to the sum of counted clock pulses; and F. repeating steps C-E for each pulse count value in the memory.

Claim 20

A method for communicating a common signal to a plurality of output elements comprising the steps of: A. storing a plurality of enabling signals in addresses of a memory; B. communicating a plurality of enabling signals stored at a memory address to selected ones of a plurality of enabling elements, each enabling signal being communicated to an associated enabling element; C. communicating, by the enabling elements, in response to the plurality of enabling signals and for so long as the enabling signal is being received by the enabling element, the common signal to the plurality of output elements; D. setting the memory to a different address; and E. repeating steps B-D for each memory address having enabling signals associated therewith.

Claim 21

A method for communicating a common signal to a plurality of output elements comprising the steps of: A. storing a plurality of enabling signals in addresses of a memory; B. communicating a plurality of enabling signals stored at a memory address to selected ones of a plurality of enabling elements, each enabling signal being communicated to an associated enabling element; C. communicating, by the enabling elements, in response to the plurality of enabling signals and for so long as the enabling signal is being received by the enabling element, the common signal to the plurality of output elements; D. setting the memory to a different address; and E. repeating steps B-D for each memory address having enabling signals associated therewith.

Claim 22

An apparatus for generating a sequence of timing signals comprising: counting means, connected to a source of clock pulses, for counting the pulses and for providing a pulse count value which is a sum of clock pulses counted; storing means for storing a plurality of pulse count values, each pulse count value representing a different sum of clock pulses counted by the counting means; selecting means, connected to the storing means, for selecting a pulse count value in the storing means; comparing means, connected to the counting means, to the storing means, and to the selecting means, for simultaneously comparing all digits in the pulse count value provided by the counting means with all digits in the selected pulse count value and for supplying a match signal when the counting means has counted a number of pulses which is the same as the selected pulse count value; generating means, connected to the determining means, for generating a timing signal in response to the match signal; and wherein the selecting means selects a different pulse count value in response to each match signal for sequentially selecting each of the plurality of pulse count values in the storing means.

Claim 23

An apparatus for generating a sequence of timing signals comprising: counting means, connected to a source of clock pulses, for counting the pulses and for providing a pulse count value which is a sum of clock pulses counted; storing means for storing a plurality of pulse count values, each pulse count value representing a different sum of clock pulses counted by the counting means; selecting means, connected to the storing means, for selecting a pulse count value in the storing means; comparing means, connected to the counting means, to the storing means, and to the selecting means, for simultaneously comparing all digits in the pulse count value provided by the counting means with all digits in the selected pulse count value and for supplying a match signal when the counting means has counted a number of pulses which is the same as the selected pulse count value; generating means, connected to the determining means, for generating a timing signal in response to the match signal; and wherein the selecting means selects a different pulse count value in response to each match signal for sequentially selecting each of the plurality of pulse count values in the storing means.

Claim 24

A method for communicating a common signal to a plurality of output elemens comprising the steps of: A. storing a plurality of enabling signals and non-enabling signals in successive addresses of a memory; B. communicating a plurality of enabling and non-enabling signals stored at an address of the memory to an associated plurality of enabling elements, each enabling element receiving one of the plurality of enabling and non-enabling signals, those enabling elements which receive an enabling signal being termed a selected enabling element; C. communicating the common signal to the plurality of enabling elements; D. coupling the plurality of output elements to the plurality of enabling elements for receiving signals therefrom, each output element being coupled to an associated enabling element, each output element coupled to a selected enabling element being termed a selected output element; E. communicating, only by the selected enabling elements, in response to the plurality of enabling signals, and for so long as the enabling signal is being received by the selected enabling elements, the common signal to the selected output elements; F. setting the memory to a different address; and G. repeating steps B-F for each of the successive memory addresses.

Claim 25

A method for communicating a common signal to a plurality of output elemens comprising the steps of: A. storing a plurality of enabling signals and non-enabling signals in successive addresses of a memory; B. communicating a plurality of enabling and non-enabling signals stored at an address of the memory to an associated plurality of enabling elements, each enabling element receiving one of the plurality of enabling and non-enabling signals, those enabling elements which receive an enabling signal being termed a selected enabling element; C. communicating the common signal to the plurality of enabling elements; D. coupling the plurality of output elements to the plurality of enabling elements for receiving signals therefrom, each output element being coupled to an associated enabling element, each output element coupled to a selected enabling element being termed a selected output element; E. communicating, only by the selected enabling elements, in response to the plurality of enabling signals, and for so long as the enabling signal is being received by the selected enabling elements, the common signal to the selected output elements; F. setting the memory to a different address; and G. repeating steps B-F for each of the successive memory addresses.

Claim 26

A method for generating a sequence of timing signals comprising the steps of: A. storing a pulse count value in an address of a first memory; B. storing a plurality of enabling signals in successive addresses of a second memory; C. communicating the plurality of enabling signals stored at a memory address to selected ones of a plurality of enabling elements, each enabling signal being communicated to an associated enabling element; D. counting pulses from a source of clock pulses to provide a sum of pulses counted; E. comparing the pulse count value to the sum of counted clock pulses; F. generating a timing signal when the pulse count value equals the sum of counted clock pulses; G. communicating the timing signal to the plurality of enabling elements; and H. communicating, by the enabling elements, in response to the plurality of enabling signals, and for so long as the enabling signal is being received by the enabling elements, the timing signal to the plurality of output elements.

Claim 27

A method for generating a sequence of timing signals comprising the steps of: A. storing a pulse count value in an address of a first memory; B. storing a plurality of enabling signals in successive addresses of a second memory; C. communicating the plurality of enabling signals stored at a memory address to selected ones of a plurality of enabling elements, each enabling signal being communicated to an associated enabling element; D. counting pulses from a source of clock pulses to provide a sum of pulses counted; E. comparing the pulse count value to the sum of counted clock pulses; F. generating a timing signal when the pulse count value equals the sum of counted clock pulses; G. communicating the timing signal to the plurality of enabling elements; and H. communicating, by the enabling elements, in response to the plurality of enabling signals, and for so long as the enabling signal is being received by the enabling elements, the timing signal to the plurality of output elements.