Amplifier circuit having crossover switching features

Claim 1

An amplifier comprising: (a) first amplifier means for amplifying a first input signal; (b) second amplifier means for amplifying a second input signal; (c) third amplifier means for amplifying a signal input therein and supplying said amplified input signal to a first load; (d) fourth amplifier means for amplifying a signal input therein and supplying said amplified input signal to a second load; (e) first switch means for supplying a output of said first amplifier means selectively to said third amplifier means and said fourth amplifier means; and (f) second switch means for supplying an output of said second amplifier means selectively to one of said third amplifier means and said fourth amplifier means, said second switch means operating with said first switch means.

Claim 8

An apparatus comprising: (a) first amplifier means for independently amplifying input signals; (b) adding means for adding said input signals amplified by said first amplifier, said amplified input signals being supplied to one terminal of said adding means and a plurality of resistors being connected in common to another terminal of said adding means; (c) a transistor for amplifying the signal added by said adding means, said signal being supplied to the emitter of said transistor; (d) buffer means for buffering an output of said transistor; (e) switching means provided between said transistor and said buffer means; and (f) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 9

An apparatus comprising: (a) first amplifier means for independently amplifying input signals; (b) adding means for adding said input signals amplified by said first amplifier, said amplified input signals being supplied to one terminal of said adding means and a plurality of resistors being connected in common to another terminal of said adding means; (c) a transistor for amplifying the signal added by said adding means, said signal being supplied to the emitter of said transistor; (d) buffer means for buffering an output of said transistor; (e) switching means provided between said transistor and said buffer means; and (f) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 10

An apparatus comprising: (a) adding means for adding input signals; (b) a transistor for amplifying the signal added by said adding means, said signal being supplied to the emitter of said transistor; (c) buffer means for buffering an output of said transistor; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 11

An apparatus comprising: (a) adding means for adding input signals; (b) a transistor for amplifying the signal added by said adding means, said signal being supplied to the emitter of said transistor; (c) buffer means for buffering an output of said transistor; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 12

An apparatus, comprising: (a) first amplifier means for independently amplifying input signals; (b) second amplifier means of a low impedance for adding and amplifying said input signals amplified by said first amplifier means; (c) buffer means for buffering an output of said second amplifier means; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said second amplifier means.

Claim 13

An apparatus, comprising: (a) first amplifier means for independently amplifying input signals; (b) second amplifier means of a low impedance for adding and amplifying said input signals amplified by said first amplifier means; (c) buffer means for buffering an output of said second amplifier means; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said second amplifier means.

Claim 14

An apparatus comprising: (a) amplifier means of a low input impedance for adding and amplifying at least two input signals; (b) buffer means for buffering an output of said amplifier means; (c) switching means provided between said amplifier means and said buffer means; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said amplifier means.

Claim 15

An apparatus comprising: (a) amplifier means of a low input impedance for adding and amplifying at least two input signals; (b) buffer means for buffering an output of said amplifier means; (c) switching means provided between said amplifier means and said buffer means; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said amplifier means.

Claim 16

An apparatus comprising: (a) resistors for adding input signals, said input signals being input to one terminal of each resistor and the other terminals of said resistors being connected in common; (b) a transistor for amplifying the signal added by said resistors, said signal being supplied to an emitter of said transistor; (c) buffer means or buffering an output of said transistor; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 17

An apparatus comprising: (a) resistors for adding input signals, said input signals being input to one terminal of each resistor and the other terminals of said resistors being connected in common; (b) a transistor for amplifying the signal added by said resistors, said signal being supplied to an emitter of said transistor; (c) buffer means or buffering an output of said transistor; and (d) means for obtaining a bias from said buffer means and for feeding back said obtained bias to said transistor.

Claim 18

An apparatus comprising: (a) amplifier means for amplifying an input signal; (b) first buffer means for amplifying and outputting a signal which is input therein; (c) second buffer means for amplifying and outputting a signal which is input therein; (d) first switch means for supplying an output of said amplifier means selectively to said first and second buffer means; and (e) second switch means for selectively supplying outputs of said first and second buffer means to said amplifier means.

Claim 19

An apparatus comprising: (a) amplifier means for amplifying an input signal; (b) first buffer means for amplifying and outputting a signal which is input therein; (c) second buffer means for amplifying and outputting a signal which is input therein; (d) first switch means for supplying an output of said amplifier means selectively to said first and second buffer means; and (e) second switch means for selectively supplying outputs of said first and second buffer means to said amplifier means.

Claim 20

An apparatus comprising: (a) first amplifier means for amplifying an input signal; (b) first and second buffer means for amplifying the amplified signal of said first amplifier means; (c) first switch means for switching the connection state of an output of said first amplifier means and said first and second buffer means; (d) second switch means for obtaining a bias to be fed back to said first amplifier means selectively from said first and second buffer means and feeding back said obtained bias selectively to said first amplifier means; (e) means for supplying an output of said first buffer means to a first load; and (f) means for supplying an output of said second buffer means to a second load.

Claim 21

An apparatus comprising: (a) first amplifier means for amplifying an input signal; (b) first and second buffer means for amplifying the amplified signal of said first amplifier means; (c) first switch means for switching the connection state of an output of said first amplifier means and said first and second buffer means; (d) second switch means for obtaining a bias to be fed back to said first amplifier means selectively from said first and second buffer means and feeding back said obtained bias selectively to said first amplifier means; (e) means for supplying an output of said first buffer means to a first load; and (f) means for supplying an output of said second buffer means to a second load.