US4792914A
Expired / Lapsed
US
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High frequency digital synthesizer with aperiodic correction optimizing the spectral purity
Assignee: Thales SA
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Filing: 1986-12-22
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Granted: 1988-12-20
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Expires: 2006-12-22
Abstract
Abstract A high frequency digital synthesizer is provided with aperiodic correction optimizing the spectral plurity, including: a generator of reference clock signals of frequency F C , a computing device, which, from a frequency increment of the signal to be synthesized, delivers, on the one hand, uncorrected pulses of frequency F Sj shifted in the time with respect to the signal of frequency F S to be synthesized by an amount Δt at most equal to 1/F and, on the other hand, a time error signal corresponding to the shift Δt and a correction circuit which is initiated by each of the frequency pulses F Sj for delaying the signal F Sj by a maximum time when the time error signal is zero by an amount equal to the maximum time reduced by the shift Δt indicated by the time error signal.
Inventors
- 👤 Luc Dartois
- 👤 Andr/e/ Roullet
- 👤 Raymond Riboni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:41
CPC Classifications
H; H03; H03L; H03L7/00; G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
234 words
A high frequency digital synthesizer with periodic corrections optimizing the spectral purity with high time precision, comprising: a generator of reference clock signals of frequency F C , a computing device which, from a frequency increment of the signal to be synthesized, delvers on the one hand uncorrected pulses of frequency F Sj shifted in time with respect to the signal to be synthesized of frequency F S by an amount Δt at most equal to 1/F C and, on the other hand, a time error signal corresponding to the shift Δt, and a correction circuit coupled to said computing device for delaying the signal F Sj by a maximum time when the timing error signal is zero and by an amount equal to the maximum time reduced by the shift Δt indicated by the timing error signal, said computing device comprising at least an accumulator register, incremented at a constant steps at the reference frequency F c of the clock signal generator having an overflow output for delivering uncorrected pulses of frequency F Sj whenever the maximum capacity of the accumulator register is reached and having an output D for delivering the contents of said accumulator register to said correction circuit and initializing said correction circuit, after each overflow of the maximum capacity of the accumulator register, by the content of said accumulator registor which represent at this time said time error signal.
Claim 2
Dependent Claim
234 words
A high frequency digital synthesizer with periodic corrections optimizing the spectral purity with high time precision, comprising: a generator of reference clock signals of frequency F C , a computing device which, from a frequency increment of the signal to be synthesized, delvers on the one hand uncorrected pulses of frequency F Sj shifted in time with respect to the signal to be synthesized of frequency F S by an amount Δt at most equal to 1/F C and, on the other hand, a time error signal corresponding to the shift Δt, and a correction circuit coupled to said computing device for delaying the signal F Sj by a maximum time when the timing error signal is zero and by an amount equal to the maximum time reduced by the shift Δt indicated by the timing error signal, said computing device comprising at least an accumulator register, incremented at a constant steps at the reference frequency F c of the clock signal generator having an overflow output for delivering uncorrected pulses of frequency F Sj whenever the maximum capacity of the accumulator register is reached and having an output D for delivering the contents of said accumulator register to said correction circuit and initializing said correction circuit, after each overflow of the maximum capacity of the accumulator register, by the content of said accumulator registor which represent at this time said time error signal.
Claim 3
Dependent Claim
85 words
The synthesizer as claimed in claim 1, wherein the increment is applied digitally to the computing device with floating point in the form of a mantissa and an exponent, the increment being transmitted to the accumulator register through a fixed point converter, a phase register and the contents of the accumulator register being transmitted to the correction circuit through a delay matrix, a shift register, a multiplier circuit and a correction register, the whole of these elements being connected together in this order in series.
Claim 4
Dependent Claim
50 words
The synthesizer as claimed in claim 2, wherein said multiplier circuit effects the multiplication of the contents of the shift register, the inverse of the multiplication of the contents of the shift register and the inverse of the mantissa of the increment applied to the input of the computing device.
Claim 5
Dependent Claim
139 words
The synthesizer as claimed in claim 3, wherein said correction circuit includes: a D-A converter coupled to the computing device for converting the time error into analog form, a ramp generator initiated by the uncorrected frequency signal obtained at the overflow output of the accumulator register, and a voltage comparator circuit coupled by a first input to the output of the ramp generator and by a second input to the output of the D-A converter through a circuit computing the difference between a given reference voltage and the voltage delivered by the output the D-A converter representing the time error, the ramp generator being reset by the output of the comparator circuit when a voltage equality is detected by the comparator circuit between the output level of the ramp generator and the output level of the difference computing circuit.
Claim 6
Dependent Claim
34 words
The synthesizer as claimed in any one of claims 2 to 4, wherein said accumulator register is formed of elementary 1 bit accumulators connected in cascade in a systolic network or pipe line structure.
Claim 7
Dependent Claim
16 words
The synthesizer as claimed in claim 5, wherein said multiplier circuit has a systolic network structure.
Claim 8
Dependent Claim
211 words
A high frequency digital synthesizer with aperiodic correction optimizing the spectral purity, including: a generator of reference clock signals of frequency F C , an accumulator register incremented at constant steps at the reference frequency F C of the clock signal generator having an overflow output for delivering a first clock signal, whenever the accumulator registor reaches its maximum capacity and having an output D for reading the contents of said accumulator register, a D-A converter coupled to output D of the accumulator register for converting the content of said accumulator register in a first voltage signal, a ramp generator initiated by by said first clock signal for delivering a second voltage signal having the form of a ramp, and a voltage comparator circuit coupled by a first input to the output of a ramp generator and by a second input to the output of the D-A converter through circuit computing the difference between a predetermined reference voltage and the first voltage signal delivered by the output of the D-A converter the ramp generator being reset by the output of the comparator circuit when voltage equality is detected by the comparator circuit between the output voltage level of the ramp generator and the output voltage level of the difference computing circuit.
Claim 9
Dependent Claim
211 words
A high frequency digital synthesizer with aperiodic correction optimizing the spectral purity, including: a generator of reference clock signals of frequency F C , an accumulator register incremented at constant steps at the reference frequency F C of the clock signal generator having an overflow output for delivering a first clock signal, whenever the accumulator registor reaches its maximum capacity and having an output D for reading the contents of said accumulator register, a D-A converter coupled to output D of the accumulator register for converting the content of said accumulator register in a first voltage signal, a ramp generator initiated by by said first clock signal for delivering a second voltage signal having the form of a ramp, and a voltage comparator circuit coupled by a first input to the output of a ramp generator and by a second input to the output of the D-A converter through circuit computing the difference between a predetermined reference voltage and the first voltage signal delivered by the output of the D-A converter the ramp generator being reset by the output of the comparator circuit when voltage equality is detected by the comparator circuit between the output voltage level of the ramp generator and the output voltage level of the difference computing circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-20 | 1992-06-20 | 1992-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-20 | 1996-06-20 | 1996-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-20 | 2000-06-20 | 2000-12-20 | $7700.00 | Window Closed / Lapsed |