US4792855A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise reducing circuit for video signal
Assignee: Victor Company of Japan Ltd
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Filing: 1988-02-12
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Granted: 1988-12-20
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Expires: 2008-02-12
Abstract
Abstract In a noise reducing circuit for a video signal comprising a first subtractor (2), a delay line (3), a second subtractor (4), a non-linear circuit (7) having a full-wave rectification circuit (7b) and a gain control circuit (7a), the gain control circuit (7a) controls a gain such that an output signal level derived from the non-linear circuit (7) increases in accordance with the increase in an output signal from the full-wave rectification circuit (7b) when the output signal level of the second subtractor (4) is within a determined extent, and that the output signal level derived from the non-linear circuit (7) decreases in accordance with the increase in the output signal from the full-wave rectification circuit (7b) when the output signal level of the second subtractor (4) is out of the determined extent.
Inventors
- 👤 Masaji Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:08
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/24; H; H04; H04N; H04N9/00; H04N9/79; H04N9/7908; H04N5/00; H04N5/14; H04N5/21; H04N5/76; H04N5/91; H04N5/911
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
114 words
A noise reducing circuit for a video signal, comprising: (a) a delaying means for delaying said video signal; (b) a first subtracting means for subtracting an output signal of said delaying means from said video signal; (c) a full-wave rectification circuit means for full-wave rectifying said output signal from said first subtracting means; (d) a gain control circuit means for controlling an amplitude of said output signal from said first subtracting means in accordance with an output signal from said full-wave rectification circuit means; and (e) a second subtracting means for subtracting an output signal of said gain control circuit from said video signal thereby producing an output signal of said noise reducing circuit.
Claim 2
Dependent Claim
114 words
A noise reducing circuit for a video signal, comprising: (a) a delaying means for delaying said video signal; (b) a first subtracting means for subtracting an output signal of said delaying means from said video signal; (c) a full-wave rectification circuit means for full-wave rectifying said output signal from said first subtracting means; (d) a gain control circuit means for controlling an amplitude of said output signal from said first subtracting means in accordance with an output signal from said full-wave rectification circuit means; and (e) a second subtracting means for subtracting an output signal of said gain control circuit from said video signal thereby producing an output signal of said noise reducing circuit.
Claim 3
Dependent Claim
105 words
A noise reducing circuit for a video signal as claimed in claim 1, wherein said gain control circuit means controls said amplitude such that said output signal of said gain control circuit means increases in accordance with the increase in an output signal from said full-wave rectification circuit means when said output signal of said first subtracting means is within a determined extent, and that said output signal of said gain control circuit means decreases in accordance with the increase in said output signal from said full-wave rectification circuit means when said output signal of said first subtracting means is out of the determined extent.
Claim 4
Dependent Claim
122 words
A noise reducing circuit for a video signal, comprising: (a) a first subtracting means responsive to said video signal; (b) a delaying means for delaying an output signal from said first subtracting means; (c) a second subtracting means for subtracting an output signal of said delaying means from said video signal; (d) a full-wave rectification circuit means for full-wave rectifying said output signal from said second subtracting means; and (e) a gain control circuit means for controlling an amplitude of said output signal from said second subtracting means in accordance with an output signal from said full-wave rectification circuit means, an output signal from said gain control circuit being fed to said first subtracting means to be subtracted from said video signal.
Claim 5
Dependent Claim
122 words
A noise reducing circuit for a video signal, comprising: (a) a first subtracting means responsive to said video signal; (b) a delaying means for delaying an output signal from said first subtracting means; (c) a second subtracting means for subtracting an output signal of said delaying means from said video signal; (d) a full-wave rectification circuit means for full-wave rectifying said output signal from said second subtracting means; and (e) a gain control circuit means for controlling an amplitude of said output signal from said second subtracting means in accordance with an output signal from said full-wave rectification circuit means, an output signal from said gain control circuit being fed to said first subtracting means to be subtracted from said video signal.
Claim 6
Dependent Claim
105 words
A noise reducing circuit for a video signal as claimed in claim 3, wherein said gain control circuit means controls said amplitude such that said output signal of said gain control circuit means increases in accordance with the increase in an output signal from said full-wave rectification circuit means when said output signal of said second subtracting means is within a determined extent, and that said output signal of said gain control circuit means decreases in accordance with the increase in said output signal from said full-wave rectification circuit means when said output signal of said second subtracting means is out of the determined extent.
Claim 7
Dependent Claim
63 words
A noise reducing circuit for a video signal as claimed in claim 4, wherein said delaying means includes first 1-H delaying means and second 1-H delaying means which are connected by a cascade connection each other, and further comprising a line switching means for switching an output signal from said first 1-H delaying means and an output signal from said first subtracting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-20 | 1992-06-20 | 1992-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-20 | 1996-06-20 | 1996-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-20 | 2000-06-20 | 2000-12-20 | $7700.00 | Window Closed / Lapsed |