Broadband signal space coupling device

Claim 2

Broadband signal switching apparatus, comprising: a crosspoint matrix including intersecting column lines, row lines, column selection lines and row selection lines; a row selection decoder including outputs connected to said row selection lines and including a row address input and a clock input; a column selection decoder including outputs connected to said column selection lines and including a column address input and a clock input; a plurality of storage cells each located at a respective intersection and each comprising a complementary metal-oxide semiconductor (CMOS) D flip-flop which includes a D input connected to a respective row selection line, a clock input connected to a respective column selection line and an output; and a pluality of switches, each of said switches located at a respective intersection and connected to the respective row and column lines and connected to and operated by the output of the respective flip-flop, each of said storage cells comprising cross-coupled CMOS inverters, one of which has its input connected to the appertaining decoder output of the one selection decoder via a CMOS transfer gate which, in turn, like a further CMOS transfoer gate inserted into the feedback path leading to this input of the one CMOS transfer inverter, has its input charged with the output signal of the appertaining decoder output of the other selection decoder and has its other input charged with the negated output signal of said decoder output.

Claim 3

Broadband signal switching apparatus, comprising: a crosspoint matrix including intersecting column lines, row lines, column selection lines and row selection lines; a row selection decoder including outputs connected to said row selection lines and including a row address input and a clock input; a column selection decoder including outputs connected to said column selection liens and including a column address input and a clock input; a plurality of storage cells each located at a respective intersection and each comprising a complementary metal-oxide semiconductor (CMOS) D flip-flop which includes a D input connected to a respective row selection line, a clock input connected to a respective column selection line and an output; and a plurality of switches, each of said switches located at a respective intersection and connected to the respective row and column lines and connected to and operated by the output of the respective flip-flop, each of said storage cells comprising a first CMOS NAND gate including a first input connected to a respective row selection line and a second input connected to the respective column selecton line of the respective intersection, said first CMOS NAND gate comprising an additional MOS transistor of the same channel type connected in series with the parallel circuit of two MOS transistors of the one channel type, and further comprising an additional MOS transistor of the same channel type connected parallel to the series circuit of the two MOS transistors of the opposite channel type, a first input connected to receive a negated output of the appertaining decoder and a further input connected to receive the output of the other decoder, said second CMOS NAND gate comprising a further MOS transistor of the same channel type connected in series with the parallel circuit of the two MOS transistors of the one channel type, and further comprising a furth MOS transistor of the same channel type connected in parallel to the series circuit of two MOS transistors of the other channel type, whereby the control electrodes of the two additional MOS transistors of each CMOS NAND gate are respectively connected to the output of the other CMOS NAND gate.

Claim 4

Broadband signal switching apparatus, comprising: a crosspoint matrix including intersecting column lines, row lines, column selection lines and row selection lines; a row selection decoder including outputs connected to said row selection lines and including a row address input and a clock input; a column selection decoder including outputs connected to said column selection liens and including a column address input and a clock input; a plurality of storage cells each located at a respective intersection and each comprising a complementary metal-oxide semiconductor (CMOS) D flip-flop which includes a D input connected to a respective row selection line, a clock input connected to a respective column selection line and an output; and a plurality of switches, each of said switches located at a respective intersection and connected to the respective row and column lines and connected to and operated by the output of the respective flip-flop, each of said storage cells comprising a first CMOS NAND gate including a first input connected to a respective row selection line and a second input connected to the respective column selecton line of the respective intersection, said first CMOS NAND gate comprising an additional MOS transistor of the same channel type connected in series with the parallel circuit of two MOS transistors of the one channel type, and further comprising an additional MOS transistor of the same channel type connected parallel to the series circuit of the two MOS transistors of the opposite channel type, a first input connected to receive a negated output of the appertaining decoder and a further input connected to receive the output of the other decoder, said second CMOS NAND gate comprising a further MOS transistor of the same channel type connected in series with the parallel circuit of the two MOS transistors of the one channel type, and further comprising a furth MOS transistor of the same channel type connected in parallel to the series circuit of two MOS transistors of the other channel type, whereby the control electrodes of the two additional MOS transistors of each CMOS NAND gate are respectively connected to the output of the other CMOS NAND gate.