Arrangement for shifting the phase of a signal passed through two parallel branches with one branch having a phase shifting network

Claim 2

A circuit arrangement for shifting the phase of a signal, comprising: two parallel branches for conveying said signal in each branch; a phase-shifting network in one of said two branches for applying a constant phase shift to said signal when passing through said one of the two branches; and means in one of said branches for controlling the amplitude of said signal and inverting the polarity of said signal.

Claim 3

A circuit arrangement as defined in claim 1, including a variable amplifier in series with said phase-shifting network for controlling the amplitude of said signal and inverting the polarity of said signal.

Claim 4

A circuit arrangement as defined in claim 1, including a variable amplifier for controlling the amplitude of said signal and inverting the polarity of said signal, said phase-shifting network being connected in one branch and said variable amplifier being connected in the other of said two parallel branches.

Claim 5

a circuit arrangement as defined in claim 1, wherein said phase-shifting network shifts the phase through +90?.

Claim 6

A circuit arrangement as defined in claim 1, including an amplifier in each one of said two branches.

Claim 7

A circuit arrangement as defined in claim 5, wherein each amplifier comprises a differential amplifier.

Claim 8

A circuit arrangement for shifting the phase of a signal, comprising: two parallel branches for conveying said signal in each branch; a phase-shifting network in one of said two branches for applying a constant phase shift to said signal when passing through said one of the two branches; and means in one of said branches for controlling the amplitude of said signal and inverting the polarity of said signal; a variable amplifier connected in series with said phase-shifting network for controlling the amplitude of said signal and inverting the polarity of said signal, said phase-shifting network shifting the phase through +90 ; an amplifier connected in each of said two branches and comprising a differential amplifier.

Claim 9

A circuit arrangement for shifting the phase of a signal, comprising: two parallel branches for conveying said signal in each branch; a phase-shifting network in one of said two branches for applying a constant phase shift to said signal when passing through said one of the two branches; and means in one of said branches for controlling the amplitude of said signal and inverting the polarity of said signal; a variable amplifier connected in series with said phase-shifting network for controlling the amplitude of said signal and inverting the polarity of said signal, said phase-shifting network shifting the phase through +90 ; an amplifier connected in each of said two branches and comprising a differential amplifier.

Claim 10

A circuit arrangement for shifting the phase of a signal, comprising: two parallel branches for conveying said signal in each branch; a phase-shifting network in one of said two branches for applying a constant phase shift to said signal when passing through said one of the two branches; and means in one of said branches for controlling the amplitude of said signal and inverting the polarity of said signal; an amplifier in each branch, said amplifier comprising a differential amplifier; a first transistor with base connected to a first input terminal for said signal; a second transistor with base connected to said first input terminal through a first resistor; a third transistor with base connected to a second input terminal of said signal; a fourth transistor with base connected to said second input terminal through a second resistor; capacitor means connected between the base of said second transistor and the base of said fourth transistor; said second transistor having an emitter connected to the emitter of said fourth transistor through a series circuit comprising a third resittor and a fourth resistor; said third transistor having an emitter connected to the emitter of said first transistor through a series circuit comprising a fifth resistor and a sixth resistor; a fifth transistor with collector connected to a junction between said third resistor and said fourth resistor; a sixth transistor with collector connected to a junction between the fifth resistor and said sixth resistor; said fifth transistor having a base connected to the base of said sixth transistor; said fifth transistor having an emitter connected to a reference potential through a seventh resistor; said sixth transistor having an emitter connected to said reference potential through an eighth resistor; a seventh transistor and an eighth transistor with emitters connected together and to the collector of said second transistor; a ninth transistor and a tenth transistor with emitters connected together and to the collector of said fourth transistor; said seventh transistor having a base connected to the base of said tenth transistor; said eighth transistor having a base connected to the base of said ninth transistor; a series circut of a ninth resistor and a tenth resistor connecting the base of said seventh transistor to the base of said eighth transistor; said first transistor and said eighth transistor as well as said tenth transistor having collectors connected together and to a voltage source through an eleventh resistor; said third transistor and said seventh transistor as well as said ninth transistor having collectors connected together and to said voltage source through a twelfth resistor; collectors of said first transistor, eighth transistor and tenth transistor being connected together at a junction comprising a first output terminal; collectors of said third transistor, seventh transistor and ninth transistor being connected together at a junction comprising a second output terminal; a first reference voltage connected to the bases of said fifth transistor and said sixth transistor; a second reference voltage connected to a junction between said ninth resistor and said tenth resistor; and a source of control voltage connected to the bases of said eighth transistor and said ninth transistor.

Claim 11

A circuit arrangement for shifting the phase of a signal, comprising: two parallel branches for conveying said signal in each branch; a phase-shifting network in one of said two branches for applying a constant phase shift to said signal when passing through said one of the two branches; and means in one of said branches for controlling the amplitude of said signal and inverting the polarity of said signal; an amplifier in each branch, said amplifier comprising a differential amplifier; a first transistor with base connected to a first input terminal for said signal; a second transistor with base connected to said first input terminal through a first resistor; a third transistor with base connected to a second input terminal of said signal; a fourth transistor with base connected to said second input terminal through a second resistor; capacitor means connected between the base of said second transistor and the base of said fourth transistor; said second transistor having an emitter connected to the emitter of said fourth transistor through a series circuit comprising a third resittor and a fourth resistor; said third transistor having an emitter connected to the emitter of said first transistor through a series circuit comprising a fifth resistor and a sixth resistor; a fifth transistor with collector connected to a junction between said third resistor and said fourth resistor; a sixth transistor with collector connected to a junction between the fifth resistor and said sixth resistor; said fifth transistor having a base connected to the base of said sixth transistor; said fifth transistor having an emitter connected to a reference potential through a seventh resistor; said sixth transistor having an emitter connected to said reference potential through an eighth resistor; a seventh transistor and an eighth transistor with emitters connected together and to the collector of said second transistor; a ninth transistor and a tenth transistor with emitters connected together and to the collector of said fourth transistor; said seventh transistor having a base connected to the base of said tenth transistor; said eighth transistor having a base connected to the base of said ninth transistor; a series circut of a ninth resistor and a tenth resistor connecting the base of said seventh transistor to the base of said eighth transistor; said first transistor and said eighth transistor as well as said tenth transistor having collectors connected together and to a voltage source through an eleventh resistor; said third transistor and said seventh transistor as well as said ninth transistor having collectors connected together and to said voltage source through a twelfth resistor; collectors of said first transistor, eighth transistor and tenth transistor being connected together at a junction comprising a first output terminal; collectors of said third transistor, seventh transistor and ninth transistor being connected together at a junction comprising a second output terminal; a first reference voltage connected to the bases of said fifth transistor and said sixth transistor; a second reference voltage connected to a junction between said ninth resistor and said tenth resistor; and a source of control voltage connected to the bases of said eighth transistor and said ninth transistor.