High density CMOS dynamic CAM cell

Claim 1

A content addressable memory comprising an array of memory cells arranged in a plurality of rows and a plurality of columns of cells, a bit line for each column of cells, a word line for each row of cells, and a match line for each row of cells; each said cell consisting essentially of: a dynamic storage element suitable for storing a data bit, an access transistor having a gate electrode coupled to the corresponding word line, said access transistor coupling the corresponding bit line to said dynamic storage element when said access transistor is enabled, and a logic gate coupled to said dynamic storage element, said corresponding bit line, and said corresponding match line, for comparing the contents of said dynamic storage element with a comparand bit on said bit line and for changing the state of said match line if said comparand bit does not match the contents of said dynamic storage element, said logic gate comprising a plurality of transistors including at least one N-channel transistor and one P-channel transistor; wherein each column of said cells is arranged so that it is symmetrically placed with respect to its neighboring columns; and the transistors in said array are located in alternating P-well and N-well regions, each P-well region and N-well region running the length of said columns and holding all the transistors of corresponding channel type for two neighboring columns of cells.