US4791384A
Expired / Lapsed
US
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Programmable function controller for use in a waveform generator system
Assignee: Harris Corp
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Filing: 1987-04-09
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Granted: 1988-12-13
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Expires: 2007-04-09
Abstract
Abstract The programmable function controller herein may be used in conjunction with a data processor and a waveform storage memory together with digital-to-analog conversion means for providing an analog waveform based on stored digital representations of the waveform in the memory. The function controller includes a plurality of registers which are initially preloaded prior to waveform generation with programmed parameter control words respecting the manner in which the waveform is to be generated. These control words are used to control logic circuitry for selecting a clock to be used by the controller for interrogating the memory to obtain the data words therefrom in a sequence representing data points on the waveform to be generated. The controller then outputs these data words to a digital-to-analog converter for providing the analog version of the waveform.
Inventors
- 👤 Peter J. Mackey
- 👤 Hakoop Hakoopian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:04
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
321 words
A programmable function controller for use in a waveform generator system which generates waveforms wherein said controller controls the generation of the waveforms in dependence upon preloaded programmed control words, said system having a plurality of clock sources, a preloaded memory, and digital to analog converter means, and said controller comprises: a plurality of data registers for respectively receiving and being preloaded prior to waveform generation with programmed parameter control words respecting the manner in which a waveform is to be generated; clock select logic means coupled to one of said registers and responsive to a control word therein for selecting one of said plurality of clock sources including at least two different internal clock sources internal to said system of different frequencies and an external clock source external to said system for providing clock pulses for use by the controller; memory address counting means sequentially incremented by said clock pulses for providing sequential addresses for use in sequentially addressing said preloaded memory to obtain therefrom data words sequentially representing data points on a waveform to be generated; means for outputting said data words to said digital-to-analog converter means for providing an analog version of said waveform; wherein said one of data registers includes a command word register for receiving and being preloaded prior to waveform generation with a control word commanding clock selection of one of said plurality of clock sources, said clock select logic means being coupled to said command word register for responding to said control word therein for selecting a clock source for use by the controller as an internal master clock; and, a sample time register for receiving and being preloaded prior to waveform generation with a sample time control word defining one of a plurality scaling factors, and sample time counting means responsive to said sample time control word and to said master clock for dividing down said master clock to obtain an addressing clock.
Claim 2
Dependent Claim
321 words
A programmable function controller for use in a waveform generator system which generates waveforms wherein said controller controls the generation of the waveforms in dependence upon preloaded programmed control words, said system having a plurality of clock sources, a preloaded memory, and digital to analog converter means, and said controller comprises: a plurality of data registers for respectively receiving and being preloaded prior to waveform generation with programmed parameter control words respecting the manner in which a waveform is to be generated; clock select logic means coupled to one of said registers and responsive to a control word therein for selecting one of said plurality of clock sources including at least two different internal clock sources internal to said system of different frequencies and an external clock source external to said system for providing clock pulses for use by the controller; memory address counting means sequentially incremented by said clock pulses for providing sequential addresses for use in sequentially addressing said preloaded memory to obtain therefrom data words sequentially representing data points on a waveform to be generated; means for outputting said data words to said digital-to-analog converter means for providing an analog version of said waveform; wherein said one of data registers includes a command word register for receiving and being preloaded prior to waveform generation with a control word commanding clock selection of one of said plurality of clock sources, said clock select logic means being coupled to said command word register for responding to said control word therein for selecting a clock source for use by the controller as an internal master clock; and, a sample time register for receiving and being preloaded prior to waveform generation with a sample time control word defining one of a plurality scaling factors, and sample time counting means responsive to said sample time control word and to said master clock for dividing down said master clock to obtain an addressing clock.
Claim 3
Dependent Claim
50 words
A programmable function controller as set forth in claim 1 including circuit means for supplying said address clock as well as said master clock to said memory address counting means, said memory address counting means being incremented by clock pulses from said master clock in synchronism with said address clock.
Claim 4
Dependent Claim
80 words
A programmable function controller as set forth in claim 2 wherein said plurality of data registers includes a START word register for receiving and being preloaded prior to waveform generation with a START word indicating a START address in said memory at which addressing is to commence for generation of a waveform, said memory address counting means being coupled to said START register and adapted to being set to a count corresponding with the address defined by said START word.
Claim 5
Dependent Claim
53 words
A programmable function controller as set forth in claim 3 wherein said plurality of data registers includes a STOP register for receiving and being preloaded prior to waveform generation with a STOP control word defining the last address in said memory at which data words are to be obtained for generating a waveform.
Claim 6
Dependent Claim
46 words
A programmable function controller as set forth in claim 4 including comparator means coupled to said address counting means and to said STOP register for providing an output signal indicative that the count in said address counter corresponds with the STOP address in said STOP resigter.
Claim 7
Dependent Claim
57 words
A programmable function controller as set forth in claim 5 including cycle counter means responsive to each said outut pulse from said comparator means for incrementing the count therein in synchronism with said master clock so that said cycle counter means provides an output count representative of the number of waveforms that have been generated thus far.
Claim 8
Dependent Claim
76 words
A programmable function controller as set forth in claim 6 wherein said plurality of data registers includes a cycle count register for receiving and being preloaded prior to waveform generation with a cycle count control word indicative of the number of waveform cycles to be generated, and comparator means for comparing the count in said cycle counter means with the cycle count word in said cycle count register and upon comparison providing a STOP output signal.
Claim 9
Dependent Claim
50 words
A programmable function controller as set forth in claim 6 wherein said plurality of data registers includes a cycle status register coupled to said cycle counter means and updated thereby so as to provide a cycle status count in the register representative of the number of cycles counted thus far.
Claim 10
Dependent Claim
68 words
A programmable function controller as set forth in claim 6 wherein said pluarlity of data registers includes a cursor register for receiving and being preloaded prior to waveform generation with a cursor control word defining a particular address, and cursor comparator means responsive to the addresse provided by said memory address counting means and to that in said cursor register and upon comparison providing a cursor output signal.
Claim 11
Dependent Claim
56 words
A programmable function controller as set forth in claim 6 wherein said plurality of data registers includes an amplitude register for receiving and being preloaded prior to waveform generation with an amplitude control word adapted to be outputted to said digital to analog converter means for controlling the magnitude of the analog version of said waveform.
Claim 12
Dependent Claim
59 words
A programmable function controller as set forth in claim 7 wherein said system includes data processing means, said controller including an internal data bus interconnected with each of said registers with said data bus adapted to be connected to said data processing means for data communication with said registers including the preloading of said control words in said registers.
Claim 13
Dependent Claim
86 words
A programmable function controller as set forth in claim 11 wherein said system includes an address bus and control signal lines, said controller iincluding a microprocessor interface means for communicating with said data processing means by way of said address bus and by way of said control signal lines, said interface means decoding addresses and control signals obtained from said data processing means for supplying WRITE and READ commands to various of said registers for writing said control words into said registers and for reading therefrom.
Claim 14
Dependent Claim
232 words
A programmable function controller for use in a waveform generator system which generates waveforms wherein said controller controls the generation of the waveforms in dependence upon preloaded programmed control words said system having a plurality of clock sources, a preloaded memory, digital to analog converter means and analog to digital converter means and said controller comprises: a plurality of data registers for respectively receiving and being preloaded prior to waveform generation with programmed parameter control words respecting the manner in which a waveform is to be generated: clock select logic means coupled to one of said registers and responsive to a control word therein for selecting one of said plurality of clock sources including at least two different clock sources internal to said system of different frequencies and an external clock source external to said system for providing clock pulses for use by the controller; memory address counting means sequentially incremented by said clock pulses for providing sequential addresses for use in sequentially addressing said preloaded memory to obtain therefrom data words sequentially representng data points on a waveform to be generated; means for outputting said data words to said digital-to-analog converter means for providing an analog version of said waveform; and, an output control register, for receiving a self test command word commanding that said analog-to-digital converter means be connected to the output of said digital-to-analog converter means for self-test analysis.
Claim 15
Dependent Claim
232 words
A programmable function controller for use in a waveform generator system which generates waveforms wherein said controller controls the generation of the waveforms in dependence upon preloaded programmed control words said system having a plurality of clock sources, a preloaded memory, digital to analog converter means and analog to digital converter means and said controller comprises: a plurality of data registers for respectively receiving and being preloaded prior to waveform generation with programmed parameter control words respecting the manner in which a waveform is to be generated: clock select logic means coupled to one of said registers and responsive to a control word therein for selecting one of said plurality of clock sources including at least two different clock sources internal to said system of different frequencies and an external clock source external to said system for providing clock pulses for use by the controller; memory address counting means sequentially incremented by said clock pulses for providing sequential addresses for use in sequentially addressing said preloaded memory to obtain therefrom data words sequentially representng data points on a waveform to be generated; means for outputting said data words to said digital-to-analog converter means for providing an analog version of said waveform; and, an output control register, for receiving a self test command word commanding that said analog-to-digital converter means be connected to the output of said digital-to-analog converter means for self-test analysis.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-13 | 1992-06-13 | 1992-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-13 | 1996-06-13 | 1996-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-13 | 2000-06-13 | 2000-12-13 | $7700.00 | Window Closed / Lapsed |