Programmable sound synthesizer

Claim 2

A circuit having an input means for receiving instructions, an output data bus, and output means for generating an audible tone, said circuit for the synthesization of a plurality of audible tones comprising: a central processor coupled to said input means for transferring and manipulating digital information in a selectively controlled and timed sequence; a frequency register coupled to said central processor for storing a tone number indicative of one of said plurality of audible tones; frequency/address generator means for generating a plurality of addresses at a rate in response to said tone number, said frequency/address generator means including digital integrating means for generating an increment in address by integrating said tone number over time and generating said increment when integration of said tone number equals a predetermined magnitude, said frequency/address generator means being coupled to said frequency register; waveform memory means for storing and writing a plurality of binary numbers indicative of waveform on said output data bus, said frequency address generator means being coupled to said waveform memory means, said waveform memory means writing said plurality of binary numbers in response to said plurality of addresses, said data bus being coupled to said output means, said output means generating one of said plurality of audible tones in response to said plurality of binary numbers coupled thereto, whereby tone frequency is determined by the rate at which said waveform memory means is collectively read and waveshape is determined by the stored contents of said waveform memory means.

Claim 3

The circuit of claim 1 wherein said frequency/address generator means and said digital integrating means includes: a clock circuit; a parallel bit adder circuit having a first input coupled to said frequency register said parallel bit adder being clocked by said clock circuit; and an accumulator having an output coupled to a second input of said adder circuit and having an input coupled to the output of said adder, a selected portion of said accumulator providing said addresses, wherein said tone number stored in said frequency register is added to said accumulator at a rate determined by said clock circuit, said selected portion of said accumulator being activated at a rate determined by the magnitude of said tone number.

Claim 4

The circuit of claim 1 further comprising: an amplitude register coupled to said central processor; and an envelope register coupled to said central processor, wherein said amplitude register stores a binary number indicative of the amplitude of one of said plurality of tones, wherein said envelope register stores a binary number indicative of the wave envelope of said one of said plurality of tones, wherein said amplitude register and envelope register are each coupled to said output means.

Claim 5

The circuit of claim 1 further comprising display means for displaying a selected one of a plurality of binary numbers is response to control from said central processor wherein said display means includes and is continuously scanned by a phase locked loop oscillator synchronized with said central processor, whereby said displays means continues to scan a display output even though said central processor is halted.

Claim 6

A circuit for synthesizing a plurality of audible tones comprising: input means for providing a plurality of inputs; output means for generating a plurality of audible tones; a central processor for selectively transferring and manipulating binary information, said central processor coupled to said input means and to said output means; a main memory coupled to said central processor for selective storing binary numbers for transfer and manipulation by said central processor; display means for visually displaying a selected binary number in response to control from said central processor; a frequency register coupled to said central processor for storing a tone number indicative of the frequency of one of said plurality of audible tones; a waveform memory for storing a plurality of binary numbers indicative of the waveform of said one audible tone; an envelope register for storing a binary number indicative of the envelope of said one audible tone; an amplitude register for storing a binary number indicative of the amplitude of said one audible tone wherein said frequency register, waveform memory, envelope register and amplitude register are each coupled to said central processor and responsive thereto; and an integrator circuit coupled to said frequency register for temporally integrating said tone number and for producing a plurality of sequential address signals; wherein said waveform memory, envelope register and amplitude register are each coupled to said output means, whereby a plurality of complex audible tones may be arbitrarily programmed and manipulated, and the frequency, waveshape, envelope and amplitude of each of said tones being independently and arbitrarily manipulatable.

Claim 7

A circuit for synthesizing a plurality of audible tones comprising: input means for providing a plurality of inputs; output means for generating a plurality of audible tones; a central processor for selectively transferring and manipulating binary information, said central processor coupled to said input means and to said output means; a main memory coupled to said central processor for selective storing binary numbers for transfer and manipulation by said central processor; display means for visually displaying a selected binary number in response to control from said central processor; a frequency register coupled to said central processor for storing a tone number indicative of the frequency of one of said plurality of audible tones; a waveform memory for storing a plurality of binary numbers indicative of the waveform of said one audible tone; an envelope register for storing a binary number indicative of the envelope of said one audible tone; an amplitude register for storing a binary number indicative of the amplitude of said one audible tone wherein said frequency register, waveform memory, envelope register and amplitude register are each coupled to said central processor and responsive thereto; and an integrator circuit coupled to said frequency register for temporally integrating said tone number and for producing a plurality of sequential address signals; wherein said waveform memory, envelope register and amplitude register are each coupled to said output means, whereby a plurality of complex audible tones may be arbitrarily programmed and manipulated, and the frequency, waveshape, envelope and amplitude of each of said tones being independently and arbitrarily manipulatable.

Claim 8

The circuit of claim 5 wherein said output means includes: a plurality of digital-to-analog converters, one said converter being coupled to each said waveform memory, envelope register and amplitude register to generate an analog waveform signal, envelope signal and amplitude signal respectively; an antilog generator coupled to said converter for generating said amplitude signal, said antilog generator for generating the antilog of said amplitude signal; a first analog multiplier circuit coupled to said converters for generating said waveform and envelope signals, said first analog multiplier circuit for generating a first product signal of said waveform and envelope signals; a second analog multiplier circuit having inputs coupled to said first multiplier circuit and antilog generator, said second analog multiplier circuit for generating a second product signal of the outputs of said first multiplier and antilog circuits; and means coupled to said second multiplier circuit for amplifying and converting said second product signal to an audible tone.

Claim 9

The circuit of claim 6 wherein said output means further comprises a calibrated gain control circuit for selectively generating a constant predetermined analog signal, and a summing circuit for adding said amplitude signal to said constant predetermined analog signal and for coupling said added signals to said antilog generator.

Claim 10

The circuit of claim 5 wherein said input and output means includes a serial input/output memory means for providing a serially accessible expanded memory accessible to said central processor.

Claim 11

The circuit of claim 5 wherein said input means includes means for providing manually set binary numbers indicative of frequency, amplitude, waveform type, envelope type, envelope attack interval, envelope sustain interval, envelope decay interval, space interval of said audible tone and sequence number of said audible tone.

Claim 12

The circuit of claim 5 wherein said display means includes means for scanning said visually displayed and selected binary number independent of the status of said central processor.