Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias

Abstract

Abstract Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.

Inventors

• 👤 Melanie M. Chow
• 👤 John E. Cronin
• 👤 William L. Guthrie
• 👤 Carter W. Kaanta
• 👤 Barbara Luther
• 👤 William J. Patrick
• 👤 Kathleen A. Perry
• 👤 Charles L. Standley

Bibliographic Details