Speed control system for DC motor

Claim 2

A motor speed control system comprising a power supply terminal, first, second and third terminals, a reference terminal, a motor connected between said power supply terminal and said first terminal, a first resistor connected between said power supply terminal and said second terminal, a second resistor connected between said first and third terminals, a third resistor connected between said second and third terminals, a first transistor having a collector-emitter path connected between said first and reference terminals, a second transistor having a collector-emitter path connected between said second and reference terminals, an error amplifier having first and second input terminals and an output terminal which is connected to bases of said first and second transistors, means coupled between said first terminal and said first input terminal of said error amplifier for generating a reference voltage thereacross, and means for connecting said third terminal to said second input terminal of said error amplifier.

Claim 3

The system as claimed in claim 1, further comprising means for supplying a bias current to said generating means without flowing via said first resistor.

Claim 4

The system as claimed in claim 1, wherein said generating means comprises a band gap regulator producing a band gap voltage.

Claim 5

The system as claimed in claim 2, wherein said generating means comprises a resistor supplied with said bias current to produce a voltage drop thereacross, said voltage drop being employed as said reference voltage.

Claim 6

The system as claimed in claim 2, further comprising a third transistor having a collector-emitter path inserted between said second terminal and said collector-emitter path of said second transistor, the base of said third transistor being connected to said first input terminal of said error amplifier.

Claim 7

A circuit combination comprising a first transistor having a collector-emitter path connected between a first terminal and a reference terminal, a second transistor having a collector-emitter path connected between a second terminal and said reference terminal, an error amplifier having first and second input terminals and an output terminal which is connected in common to bases of said first and second transistors, a bias current source connected between a power terminal and said first input terminal of said error amplifier and producing a bias current, a reference voltage circuit connected between said first terminal and said first input terminal of said error amplifier and generating a reference voltage in response to said bias current, a motor connected between said first terminal and said power terminal, a first resistor connected between said second terminal and said power terminal, second and third resistors connected in series between said first and second terminals, and means for level-shifting a potential at the node of said second and third resistors to supply the level-shifted potential to said second input terminal of said error amplifier.

Claim 8

A circuit combination comprising a first transistor having a collector-emitter path connected between a first terminal and a reference terminal, a second transistor having a collector-emitter path connected between a second terminal and said reference terminal, an error amplifier having first and second input terminals and an output terminal which is connected in common to bases of said first and second transistors, a bias current source connected between a power terminal and said first input terminal of said error amplifier and producing a bias current, a reference voltage circuit connected between said first terminal and said first input terminal of said error amplifier and generating a reference voltage in response to said bias current, a motor connected between said first terminal and said power terminal, a first resistor connected between said second terminal and said power terminal, second and third resistors connected in series between said first and second terminals, and means for level-shifting a potential at the node of said second and third resistors to supply the level-shifted potential to said second input terminal of said error amplifier.

Claim 9

The circuit combination as claimed in claim 6, wherein said level shifting means comprises a third transistor and a current source, said third transistor having a base connected to said node, a collector connected to said power terminal and an emitter connected to said second input terminal of said error amplifier, and said current source connected between the emitter of said third transistor and said reference terminal.

Claim 10

An integrated circuit device for a motor speed control, comprising first, second, third, fourth and fifth terminals, first and second transistors each having a base, an emitter and a collector, first means for connecting the collector of said first transistor to said first terminal, second means for connecting the collector of said second transistor to said second terminal, third means for connecting the emitters of said first and second transistors to said fourth terminal, a differential amplifier having first and second input terminals and an output terminal, fourth means for connecting said output terminal of said differential amplifier to the bases of said first and second transistors, fifth means for connecting said first input terminal of said differential amplifier to said third terminal, a reference voltage circuit connected between said first terminal and said second input terminal of said differential amplifier, and a bias current source connected between said fifth terminal and said second input terminal of said differential amplifier.

Claim 11

An integrated circuit device for a motor speed control, comprising first, second, third, fourth and fifth terminals, first and second transistors each having a base, an emitter and a collector, first means for connecting the collector of said first transistor to said first terminal, second means for connecting the collector of said second transistor to said second terminal, third means for connecting the emitters of said first and second transistors to said fourth terminal, a differential amplifier having first and second input terminals and an output terminal, fourth means for connecting said output terminal of said differential amplifier to the bases of said first and second transistors, fifth means for connecting said first input terminal of said differential amplifier to said third terminal, a reference voltage circuit connected between said first terminal and said second input terminal of said differential amplifier, and a bias current source connected between said fifth terminal and said second input terminal of said differential amplifier.

Claim 12

The integrated circuit device as claimed in claim 8, wherein said second means comprises a third transistor having an emitter connected to the collector of said second transistor, a collector connected to said second terminal and a base connected to said second input terminal of said differential amplifier.

Claim 13

The integrated circuit device as claimed in claim 8, wherein said fifth means comprises a third transistor having a base connected to said third terminal, an emitter connected to said first input terminal of said differential amplifier and a collector connected to said fifth terminal.