Preamble search and synchronizer circuit

Claim 2

A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and for synchronizing it with a clock signal associated with a starLAN coded data transceiver, said preamble search and synchronizer circuit comprising: input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal; synchronizer start means responsive to the complement of the data input signals and the uncomplemented clock signal for generating a start signal which is synchronized with the uncomplemented clock signal; counter means responsive to the start signal and the complement of the clock signal for generating a gated clock signal; and pattern detector means responsive to the start signal, the data input signals and the gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of the preamble pattern.

Claim 3

A preamble search and synchronizer as claimed in claim 1, wherein said synchronizer start means includes first and second D-type flip-flops, said first flip-flop receiving the complement of the data input signals at its clock terminal and its true output connected to the data input of said second flip-flop, said second flip-flop receiving the clock signal at its clock terminal and its true output connected to said counter means and said pattern detector means to provide the start signal.

Claim 4

A preamble search and synchronizer circuit as claimed in claim 2, wherein said counter means comprises a synchronous binary counter formed of first, second and third J-K flip-flops and a NAND logic gate to provide the gated clock signal.

Claim 5

A preamble search and synchronizer circuit as claimed in claim 3, wherein said pattern detector means comprises a three-stage shift register formed of third, fourth and fifth D-type flip-flops whose clock terminals are connected to receive the gated clock signal.

Claim 6

A preamble search and synchronizer circuit as claimed in claim 4, wherein said pattern detector circuit further comprises decoder means for decoding the true and complement outputs of said third, fourth and fifth D-type flip-flops, and an output latch connected to the output of said decoding means for providing the synchronized output signal.

Claim 7

A preamble search and synchronizer circuit as claimed in claim 5, wherein said decoder means is formed of an AND logic gate and said output latch is formed of a sixth D-type flip-flop, the true output of said sixth D-type flip-flop providing the synchronized output signal and which makes a low-to-high transition upon detection of the preamble pattern.

Claim 8

A preamble search and synchronizer circuit as claimed in claim 6, further comprising resetting means responsive to the complement output of the fifth D-type flip-flop of said shift register for automatically resetting said synchronizer start means when the preamble pattern is not detected and the true output of the said fifth D-type flip-flop makes a high-to-low transition.

Claim 9

A preamble search and synchronizer circuit as claimed in claim 7, wherein said resetting means is formed of a seventh D-type flip-flop having its data input connected to a supply potential, its clock terminal connected to the complement output of the fifth D-type flip-flop, and its complement output coupled to the clock terminal of said first and second D-type flip-flops.

Claim 10

A preamble search and synchronizer circuit as claimed in claim 8, wherein said synchronizer start means further comprises inhibiting means for preventing further operation of said preamble search and synchronizer circuit for a fixed period of time after the end of transmission of a message.

Claim 11

A preamble search and synchronizer circuit as claimed in claim 1, wherein said preamble search and synchronizer circuit is formed as a part of a single monolithic integrated circuit.

Claim 12

A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and for synchronizing it with a clock signal associated with a starLAN coded data transceiver, said preamble search and synchronizer circuit comprising: input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal; synchronizer start means responsive to the complement of the data input signals and the uncomplemented clock signal for generating a start signal which is synchronized with the uncomplemented clock signal; counter means responsive to the start signal and the complement of the clock signal for generating a first gated clock signal and a second gated clock signal; pattern detector means responsive to the start signal, the data input signals, the first gated clock signal and the second gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of the preamble pattern; and said pattern detector means including shift register means connected to receive the first gated clock signal for shifting the sampled input signals and decoder means connected to the outputs of said shift register means and the second gated clock signal for detecting the preamble pattern.

Claim 13

A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and for synchronizing it with a clock signal associated with a starLAN coded data transceiver, said preamble search and synchronizer circuit comprising: input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal; synchronizer start means responsive to the complement of the data input signals and the uncomplemented clock signal for generating a start signal which is synchronized with the uncomplemented clock signal; counter means responsive to the start signal and the complement of the clock signal for generating a first gated clock signal and a second gated clock signal; pattern detector means responsive to the start signal, the data input signals, the first gated clock signal and the second gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of the preamble pattern; and said pattern detector means including shift register means connected to receive the first gated clock signal for shifting the sampled input signals and decoder means connected to the outputs of said shift register means and the second gated clock signal for detecting the preamble pattern.

Claim 14

a preamble search and synchronizer as claimed in claim 11, wherein said synchronizer start means includes first and second D-type flip-flops, said first flip-flop receiving the complement of the data input signals at its clock terminal and its true output connected to the data input of said second flip-flop, said second flip-flop receiving the clock signal at its clock terminal and its true output connected to said counter means and said pattern detector means to provide the start signal.

Claim 15

A preamble search and synchronizer circuit as claimed in claim 12, wherein said counter means comprises a synchronous binary counter formed of first, second and third J-K flip-flops and a NAND logic gate to provide the gated clock signal.

Claim 16

A preamble search and synchronizer circuit as claimed in claim 13, wherein said shift register means is formed of third, fourth and fifth D-type flip-flops whose clock terminals are connected to receive the first gated clock signal.

Claim 17

A preamble search and synchronizer circuit as claimed in claim 14, further comprising resetting means responsive to the complement output of the fifth D-type flip-flop of said shift register means for automatically resetting said synchronizer start means when the preamble pattern is not detected and the true output of the said fifth D-type flip-flop makes a high-to-low transition.

Claim 18

A preamble search and synchronizer circuit as claimed in claim 15, wherein said resetting means is formed of a sixth D-type flip-flop having its data input connected to a supply potential, its clock terminal connected to the complement output of the fifth D-type flip-flop, and its complement output coupled to the clock terminal of said first and second D-type flip-flops.

Claim 19

A preamble search and synchronizer circuit as claimed in claim 16, wherein said synchronizer start means further comprises inhibiting means for preventing further operation of said preamble search and synchronizer circuit for a fixed period of time after the end of transmission of a message.

Claim 20

A preamble search and synchronizer circuit as claimed in claim 11, wherein said preamble search and synchronizer circuit is formed as a part of a single monolithic integrated circuit.

Claim 21

A preamble search and synchronizer circuit comprising: input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal; synchronizer start means responsive to the uncomplemented clock signal and complement of the data input signals for generating a start signal which is synchronized with the uncomplemented clock signal; counter means responsive to the start signal and the complement of the clock signal for generating a gated clock signal; and pattern detector means responsive to the start signal, the data input signals and the gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of a preamble pattern contained within the data input signals.

Claim 22

A preamble search and synchronizer circuit comprising: input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal; synchronizer start means responsive to the uncomplemented clock signal and complement of the data input signals for generating a start signal which is synchronized with the uncomplemented clock signal; counter means responsive to the start signal and the complement of the clock signal for generating a gated clock signal; and pattern detector means responsive to the start signal, the data input signals and the gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of a preamble pattern contained within the data input signals.

Claim 23

A preamble search and synchronizer circuit as claimed in claim 19, wherein said preamble search and synchronizer circuit is formed as a part of a single monolithic integrated circuit.