Data processing apparatus with fixed address space

Claim 2

In a system comprising a processor, memory addressing means defining a finite memory address space, and an indefinite plurality of memory containing modules connectable into said address space, the improvement comprising: each of said modules having an identification indicium which is different from that of any of the other of said plurality of modules, each of said modules having memory address decoding means responsive to addresses in one common segment of said address space, each of said modules having an identifier register writable by said processor, and each of said modules having comparison means sensitive to the contents of its said identifier register and operative upon a predetermined relationship of the contents of said register to the indicium of the module to enable said memory on that module to respond to said addresses in said one common segment so long as that module is enabled and to the exclusion of the others of said modules, whereby said modules effectively occupy said segment of said address space selectively and one at a time.

Claim 3

A system in accordance with claim 1, further comprising means defining a table identifying those said modules acutally connected into said system and the location, outside said address space, defining the current status of each said connected module.

Claim 4

A system in accordance with claim 2, further including means utilizing said table to examine the status of the devices listed in the table for a given status and to broadcast to said identifier registers an indicator value having said predetermined relationship to the said identification indicium of devices having said status, one at a time, whereby the thus selected devices are enabled one at a time.

Claim 5

Data processing apparatus having a central processor connected to a plurality of ports to any or all of which may be attached a selection from a group of compatible devices, each incorporating means signifying its individual identity in terms distinguishing it from each of the others of said devices, some of the devices of the group including memory and a status register, requests for service from attached devices being ORed to the central processor, the central processor being arranged on power up and system reset to initialize and determine the function and location of the currently attached devices, the central processor including a memory accessing facility for accessing memory in terms of a fixed size address space and a register accessing facility for accessing individual registers in attached devices using register addresses which are independent of the memory address space, characterized in that (a) the initializing facility includes means for generating a (first) list associating the individual identity of each attached device including memory with the register address of the status register of that device; (b) the central processor is arranged to respond to a request for service by accessing the list and by indexing through the list, examining the status of each listed device in turn to determine if the currently examined device requested service and, if so, broadcasting the identity of that device followed by one or more memory addresses; and (c) each device having memory also including means for comparing each brodcast identity with the identity of the device and, on detecting equality, to latch the associated memory enabled to the exclusion of all of the others of said devices until the first detected inequality, and in that (d) the enabled device appears as a single entity to the central processor and occupies a single window in the address space which is common to all of said devices but used by them only one at a time.

Claim 6

Data processing apparatus having a central processor connected to a plurality of ports to any or all of which may be attached a selection from a group of compatible devices, each incorporating means signifying its individual identity in terms distinguishing it from each of the others of said devices, some of the devices of the group including memory and a status register, requests for service from attached devices being ORed to the central processor, the central processor being arranged on power up and system reset to initialize and determine the function and location of the currently attached devices, the central processor including a memory accessing facility for accessing memory in terms of a fixed size address space and a register accessing facility for accessing individual registers in attached devices using register addresses which are independent of the memory address space, characterized in that (a) the initializing facility includes means for generating a (first) list associating the individual identity of each attached device including memory with the register address of the status register of that device; (b) the central processor is arranged to respond to a request for service by accessing the list and by indexing through the list, examining the status of each listed device in turn to determine if the currently examined device requested service and, if so, broadcasting the identity of that device followed by one or more memory addresses; and (c) each device having memory also including means for comparing each brodcast identity with the identity of the device and, on detecting equality, to latch the associated memory enabled to the exclusion of all of the others of said devices until the first detected inequality, and in that (d) the enabled device appears as a single entity to the central processor and occupies a single window in the address space which is common to all of said devices but used by them only one at a time.

Claim 7

Apparatus as claimed in claim 4 wherein some of the devices of the group which include memory have stored therein, independent of powering up and system reset, routines defining system functions which are identifiable in terms of system function, the initializing facility including means for generating a second list associating each device providing system function with the individual identity of the providing device, the central processing unit obtaining any one of the listed system functions by accessing the second list by system function and broadcasting the associated device identity followed by one or more memory addresses.

Claim 8

Apparatus as claimed in claim 4 or claim 5 wherein the initializing facility is arranged to retain the generated list or lists in writable memory on one of the attached devices.