Apparatus for parallel-processing image data

Claim 2

An image processing apparatus comprising: image signal generation means for generating, in parallel digital image signals having a plurality of pixels; division means for dividing the digital image signals generated in parallel by said image signal generating means into a plurality of blocks; and a plurality of image processors for parallel-processing by block the divided digital image signal, each of said plurality of image processors being connected for receiving, an an input for processing both the digital image signal of the pixel to be parallel-processed and the digital image signal of the pixel adjacent the pixel to be parallel processed.

Claim 3

An image processing apparatus according to claim 1, further comprising: output means for outputting processing results of said plurality of image processors, wherein said output means has converting means for converting the processing result of said image processors from parallel into series.

Claim 4

An image processing apparatus according to claim 1, wherein each of said image processors has an operation control portion, a first memory portion for storing therein digital image information converted by an analog to digital converting portion, and a second memory portion for storing therein a procedure for two-dimensionally image-processing said digital image information and a control procedure for controlling said operation control portion and said first memory portion.

Claim 5

An image processing apparatus according to claim 1, wherein said image signal generating means comprises reading means for reading an original image.

Claim 6

An image processing apparatus according to claim 4, wherein said reading means includes a photoelectric converting portion, said plurality of image processors and said converting means being arranged on one base plate.

Claim 7

An image processing apparatus comprising means for dividing a read image signal from a reading sensor into m blocks, and m image processors each for receiving as an input a read image signal for each of said divided blocks and for parallel-image-processing each said read image signal the nth image processor being connected for receiving as inputs, in addition to the read image signal of the nth block, a read image signal for several pixels each of which adjoins and is continuous to the nth block, out of the read image signal of the (n-1)th block and the read image signal of the (n+1)th block, respectively, where 1≦n≦m.

Claim 8

An image processing apparatus comprising means for dividing a read image signal from a reading sensor into m blocks, and m image processors each for receiving as an input a read image signal for each of said divided blocks and for parallel-image-processing each said read image signal the nth image processor being connected for receiving as inputs, in addition to the read image signal of the nth block, a read image signal for several pixels each of which adjoins and is continuous to the nth block, out of the read image signal of the (n-1)th block and the read image signal of the (n+1)th block, respectively, where 1≦n≦m.

Claim 9

An image processing apparatus according to claim 6, wherein each said image processor comprises a monolithic integrated circuit having input terminals on the four sides thereof, said dividing means is a wiring pattern to said integrated circuit, the read image signal of the corresponding block of said image processor is input to a terminal on one of said four sides which is not opposed to the remaining sides, and the read image signal from each adjacent block is input to terminals on two of said four sides which are opposed to each other.

Claim 10

An image processing apparatus according to claim 6, wherein each said image processor comprises a monolithic integrated circuit having input terminals on the four sides thereof, said dividing means is a wiring pattern to said integrated circuit, and the read image signal of the corresponding block of each said image processor and the read image signal from each adjacent block are input to terminals on two of said four sides which are opposed to each other.

Claim 11

An image processing apparatus comprising image reading sensors arranged in a row in a main scan direction, samples signal output means for producing a sample signal while relatively moving a read image in a direction orthogonal to the row of said image reading sensors, and a plurality of image processors for divisionally receiving the image information from said sensors as an input and for image-processing the image information, each of said image processors having therein an analog to digital converting portion for digitalizing outputs of said reading sensors and a processing portion for processing a digitalized image signal, each of said image processors including said analog to digital conerting portion and said processing portion being on a single chip, and starting analog to digital conversion substantially at one time in accordance with said sample signal.

Claim 12

An image processing apparatus comprising image reading sensors arranged in a row in a main scan direction, samples signal output means for producing a sample signal while relatively moving a read image in a direction orthogonal to the row of said image reading sensors, and a plurality of image processors for divisionally receiving the image information from said sensors as an input and for image-processing the image information, each of said image processors having therein an analog to digital converting portion for digitalizing outputs of said reading sensors and a processing portion for processing a digitalized image signal, each of said image processors including said analog to digital conerting portion and said processing portion being on a single chip, and starting analog to digital conversion substantially at one time in accordance with said sample signal.

Claim 13

An image processing apparatus according to claim 9, wherein each said image processor comprises a monolithic integrated circuit having an operation control portion, a first memory portion for storing therein digital image information converted by the analog to digital converting portion, and a second memory portion for storing therein a procedure for two-dimensionally image-processing said digital image information and a control procedure for controlling said operation control portion and said first memory portion.

Claim 14

An image processing apparatus according to claim 10, wherein the image processing procedure divides the digital image information stored in said first memory portion into blocks, recognizes the image tones of said divided blocks and binarizes the central pixel of said blocks on the basis of the result of the image tone recognition.