Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
An FDM demultiplexer comprising: means for converting an N-channel FDM (frequency division multiplexed) signal into complex signals of baseband frequencies, the channels of said FDM signal being spaced at frequency Δf; analog-to-digital converting means for converting said complex signals into digital samples having a frequency NΔf; serial-to-parallel converter means for converting a series of N digital samples of said complex signals into N parallel digital signals; a plurality of first finite impulse response (FIR) subfilter means for respectively filtering said parallel digital signals at frequency Δf to produce a first series of filtered digital signals from each of said first FIR subfilter means; (m-1) groups of second FIR subfilter means, the second FIR subfilter means of each of said (m-1) groups respectively filtering said parallel digital signals at frequency Δf and delivering a second series of filtered digital samples from each of said second FIR subfilter means at timing displaced with respect to said first series by a/mΔf, where a is an integer ranging from unity to (m-1) and m is an integer equal to or greater than 2; a plurality of adders for respectively summing outputs of said first FIR subfilter means with outputs of said second FIR subfilter means to produce N summation outputs at frequency mΔf; and an N-point Fast Fourier Transform (FFT) processor connected to said adders for performing fast Fourier transform on said N summation outputs at frequency mΔf.
Claim 2
Dependent Claim
234 words
An FDM demultiplexer comprising: means for converting an N-channel FDM (frequency division multiplexed) signal into complex signals of baseband frequencies, the channels of said FDM signal being spaced at frequency Δf; analog-to-digital converting means for converting said complex signals into digital samples having a frequency NΔf; serial-to-parallel converter means for converting a series of N digital samples of said complex signals into N parallel digital signals; a plurality of first finite impulse response (FIR) subfilter means for respectively filtering said parallel digital signals at frequency Δf to produce a first series of filtered digital signals from each of said first FIR subfilter means; (m-1) groups of second FIR subfilter means, the second FIR subfilter means of each of said (m-1) groups respectively filtering said parallel digital signals at frequency Δf and delivering a second series of filtered digital samples from each of said second FIR subfilter means at timing displaced with respect to said first series by a/mΔf, where a is an integer ranging from unity to (m-1) and m is an integer equal to or greater than 2; a plurality of adders for respectively summing outputs of said first FIR subfilter means with outputs of said second FIR subfilter means to produce N summation outputs at frequency mΔf; and an N-point Fast Fourier Transform (FFT) processor connected to said adders for performing fast Fourier transform on said N summation outputs at frequency mΔf.
Claim 3
Dependent Claim
70 words
An FDM demultiplexer as claimed in claim 1, wherein said second FIR subfilter means are divided into first and second groups, outputs of said second FIR subfilter means of said first group leading outputs of said first FIR subfilter means by a·N/m digital samples and outputs of said second FIR subfilter means of said second group lagging behind the outputs of said first FIR subfilter means by a·N/m digital samples.
Claim 4
Dependent Claim
58 words
An FDM demultiplexer as claimed in claim 1, further comprising: first and second frequency converter means for respectively converting first and second outputs of said FFT processor into a first signal of a higher frequency range and a second signal of a lower frequency range; and means for combining said first and second signals into a wideband signal.
Claim 5
Dependent Claim
52 words
An FDM demultiplexer as claimed in claim 3, wherein said combining means additionally combines a third output of said FFT processor with said first and second signals so that said wideband signal has a bandwidth three times the bandwidth of each of said first, second and third outputs of said FFT processor.
Claim 6
Dependent Claim
39 words
An FDM demultiplexer as claimed in claim 3, further comprising switching means for selectively coupling said first and second outputs of said FFT processor to said first and second frequency converter means, respectively, in response to a control signal.
Claim 7
Dependent Claim
43 words
An FDM demultiplexer as claimed in claim 3, further comprising first and second FIR low-pass filter means for respectively filtering said first and second outputs of said FFT processor and applying the filtered outputs to said first and second frequency converter means, respectively.