Patent US4785423A successfully refreshed from Google Patents.
US4785423A
Expired / Lapsed
US
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Current limited epld array
Assignee: Altera Corp
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Filing: 1987-01-22
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Granted: 1988-11-15
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Expires: 2007-01-22
Abstract
Abstract An improved architecture for an EPROM PAL utilizing two bit lines is disclosed. The drains of the EPROM cells of a given column of an array are coupled together to a first bit line. The first line is coupled to a sensing circuit. The sources of the EPROM cells are coupled together to a second bit line which is then coupled through a current limiting transistor. The gate of the transistor is coupled to the first bit line to receive a feedback signal for controlling the current on the bit lines. The current limiting feature provides for shorter transition periods between "on" and "off" states which results in an improved speed performance of the device.
Inventors
- 👤 Joseph A. Skupnjak
- 👤 Abid Asghar
- 👤 Kirby S. Hallenbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/24
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
132 words
An erasable programmable logic device comprising: a plurality of memory cells coupled to vrious input signal lines; a first bit line coupled to a first side of each of said memory cells; a second bit line coupled to a second side of each of said memory cells; a sensing amplifier coupled to said first bit line such that said sensing amplifier monitors current flow on said first bit line; current controlling means coupled to said second bit line wherein total current flow through said plurality of memory cells also flows through said sensing amplifier and said current controlling means; said current controlling means also coupled to said sensing amplifier such that said current flow determines a drive of said current controlling means for maintaining a predetermined current limit on said current flow.
Claim 2
Dependent Claim
132 words
An erasable programmable logic device comprising: a plurality of memory cells coupled to vrious input signal lines; a first bit line coupled to a first side of each of said memory cells; a second bit line coupled to a second side of each of said memory cells; a sensing amplifier coupled to said first bit line such that said sensing amplifier monitors current flow on said first bit line; current controlling means coupled to said second bit line wherein total current flow through said plurality of memory cells also flows through said sensing amplifier and said current controlling means; said current controlling means also coupled to said sensing amplifier such that said current flow determines a drive of said current controlling means for maintaining a predetermined current limit on said current flow.
Claim 3
Dependent Claim
13 words
The device of claim 1, wherein said current controlling means is a transistor.
Claim 4
Dependent Claim
15 words
The device of claim 2, wherein said memory cells are electrically programmable read only memories.
Claim 5
Dependent Claim
157 words
An erasable programmable logic device having a plurality of electrically programmable read only memory (EPROM) cell transistors, comprising: a sensing amplifier coupled to a voltage source; a first bit line coupled to said sensing amplifier and to drains of said EPROM cells; a second bit line coupled to sources of said EPROM cells; a current limiting transistor coupled in series between said second bit line and a return for said voltage source wherein total current flow through said plurality of memory cell transistors also flows serially through said sensing amplifier and said current limiting transistor; said current limiting transistor having its gate coupled to said sensing amplifier for receiving a feedback signal which determines a gate drive of said current limiting transistor such that said current limiting transistor maintains a predetermined current limit of said current flow to control discharge of said first bit line which provides for a faster response speed of said memory cell transistors.
Claim 6
Dependent Claim
157 words
An erasable programmable logic device having a plurality of electrically programmable read only memory (EPROM) cell transistors, comprising: a sensing amplifier coupled to a voltage source; a first bit line coupled to said sensing amplifier and to drains of said EPROM cells; a second bit line coupled to sources of said EPROM cells; a current limiting transistor coupled in series between said second bit line and a return for said voltage source wherein total current flow through said plurality of memory cell transistors also flows serially through said sensing amplifier and said current limiting transistor; said current limiting transistor having its gate coupled to said sensing amplifier for receiving a feedback signal which determines a gate drive of said current limiting transistor such that said current limiting transistor maintains a predetermined current limit of said current flow to control discharge of said first bit line which provides for a faster response speed of said memory cell transistors.
Claim 7
Dependent Claim
36 words
The device of claim 4, wherein said EPROM cells form one column of a row-column matrix array; said array having a duplication of said bit lines, sensing amplifier and current limiting transistor for each said column.
Claim 8
Dependent Claim
26 words
The device of claim 5, wherein said second bit line is coupled to a drain and a ground coupled to source of said current limiting transistor.
Claim 9
Dependent Claim
136 words
In an erasable programmable logic device having a plurality of electrically programmable read only memory having a plurality of cells arranged in a row and column matrixed array wherein each column having cell transistors which have first sides coupled to a bit line which is coupled to a sensing amplifier and gates coupled to various input lines and improvement comprising: a current controlling transistor coupled serially between second sides of said cell transistors and ground and having its gate drive coupled to monitor current flow on said bit line such that said current controlling transistor limits maximum value of said current flow on said bit line to a predetermined value, wherein control of said maximum value of said current controls discharge of said bit line which provides for a faster response speed of said cell transistors.
Claim 10
Dependent Claim
136 words
In an erasable programmable logic device having a plurality of electrically programmable read only memory having a plurality of cells arranged in a row and column matrixed array wherein each column having cell transistors which have first sides coupled to a bit line which is coupled to a sensing amplifier and gates coupled to various input lines and improvement comprising: a current controlling transistor coupled serially between second sides of said cell transistors and ground and having its gate drive coupled to monitor current flow on said bit line such that said current controlling transistor limits maximum value of said current flow on said bit line to a predetermined value, wherein control of said maximum value of said current controls discharge of said bit line which provides for a faster response speed of said cell transistors.
References Cited (Backward Citations)
US4371956A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |