BIMOS memory sense amplifier system

Claim 2

A circuit comprising: a first supply voltage terminal; a second supply voltage terminal; a first input terminal; a second input terminal; a first enable terminal; a second enable terminal; a first output terminal; a second output terminal; first means coupled between said first and second supply voltage terminals and coupled to said first and second input terminals for differentially providing first and second signals; second means coupled between said first supply voltage terminal and said first output terminal and coupled to said first means and responsive to said first signal for providing a first output; third means coupled between said first supply voltage terminal and said second output terminal and coupled to said first means and responsive to said second signal for providing a second output; fourth means coupled between said first output terminal and said first input terminal and coupled to said first enable terminal for selectively clamping said input terminal; and fifth means coupled between said second output terminal and said second input terminal and coupled to said second enable terminal for selectively clamping said input terminal.

Claim 3

The circuit according to claim 1 wherein said first means comprises: a first resistor; a second resistor; a current source; a first transistor having a collector coupled to said first supply voltage terminal by said first resistor and to said second means, a base coupled to said first input terminal, and an emitter coupled to said second supply voltage terminal by said current source; and a second transistor having a collector coupled to said first supply voltage terminal by said second resistor and to said third means, a base coupled to said second input terminal, and an emitter coupled to said second supply voltage terminal by said current source.

Claim 4

The circuit according to claim 2 wherein said second means comprises a third transistor having a collector coupled to said first supply voltage terminal, a base coupled to said collector of said first transistor, and an emitter coupled to said first output terminal and said fourth means.

Claim 5

The circuit according to claim 3 wherein said fourth means comprises a fourth transistor having a drain coupled to said emitter of said third transistor, a gate coupled to said first enable terminal, and a source coupled to said base of said first transistor.

Claim 6

The circuit according to claim 3 wherein said third means comprises a fourth transistor having a collector coupled to said first supply voltage terminal, a base coupled to said collector of said second transistor, and an emitter coupled to said second output terminal and said fifth means.

Claim 7

The circuit according to claim 5 wherein said fifth means comprises a fifth transistor having a drain coupled to said emitter of said fourth transistor, a gate coupled to said second enable terminal, and a source coupled to said base of said second transistor.

Claim 8

The circuit according to claim 6 wherein said fourth means comprises a sixth transistor having a drain coupled to said emitter of said third transistor, a gate coupled to said first enable terminal, and a source coupled to said base of said first transistor.

Claim 9

A memory circuit comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells, wherein each of said memory cells are uniquely coupled between one of said pair of bit lines and to one of said plurality of word lines, each of said memory cells having a read mode and a write mode; first means coupled to said plurality of word lines for selecting one of said word lines; second means coupled to said plurality of pairs of bit lines for selecting one of said pair of bit lines; and a plurality of third means, each of said third means coupled to a pair of bit lines for sensing the voltage on said pair of bit lines for determining the mode of said memory cell uniquely coupled thereto, each of said third means comprising: a first output terminal; a second output terminal; fourth means coupled to said pair of bit lines for differentially providing first and second signals; fifth means coupled between said first means and said first output terminal and responsive to said first signal for providing a first output; sixth means coupled between said first means and said second output terminal and responsive to said second signal for providing a second output; seventh means coupled between one of said bit lines and said first output terminal for selectively clamping a voltage on said bit line during said read mode; and eighth means coupled between said another of said bit lines and said second output terminal for selectively clamping a voltage on said bit line during said read mode.

Claim 10

A memory circuit comprising: a plurality of word lines; a plurality of pairs of bit lines; a plurality of memory cells, wherein each of said memory cells are uniquely coupled between one of said pair of bit lines and to one of said plurality of word lines, each of said memory cells having a read mode and a write mode; first means coupled to said plurality of word lines for selecting one of said word lines; second means coupled to said plurality of pairs of bit lines for selecting one of said pair of bit lines; and a plurality of third means, each of said third means coupled to a pair of bit lines for sensing the voltage on said pair of bit lines for determining the mode of said memory cell uniquely coupled thereto, each of said third means comprising: a first output terminal; a second output terminal; fourth means coupled to said pair of bit lines for differentially providing first and second signals; fifth means coupled between said first means and said first output terminal and responsive to said first signal for providing a first output; sixth means coupled between said first means and said second output terminal and responsive to said second signal for providing a second output; seventh means coupled between one of said bit lines and said first output terminal for selectively clamping a voltage on said bit line during said read mode; and eighth means coupled between said another of said bit lines and said second output terminal for selectively clamping a voltage on said bit line during said read mode.

Claim 11

The circuit according to claim 8 further comprising ninth means coupled between said pair of bit lines for clamping said bit lines at a clamping voltage when said bit lines are not selected.

Claim 12

The circuit according to claim 9 wherein said ninth means comprises: a voltage terminal for receiving said clamping voltage; a first transistor coupled between one of said bit lines and said voltage terminal and having a gate coupled to said second means and responsive to a column select signal; and a second transistor coupled between the other of said bit lines and said voltage terminal and having a gate coupled to said second means and responsive to said column select signal.

Claim 13

The circuit according to claim 8 wherein said fourth means comprises: a first resistor; a second resistor; a current source; a first transistor having a collector coupled to a first voltage by said first resistor and to said fifth means, a base coupled to one of said bit lines, and an emitter coupled to a second voltage by said current source; and a second transistor having a collector coupled to said first voltage by said second resistor and to said sixth means, a base coupled to another of said bit lines, and an emitter coupled to said second voltage terminal by said current source.

Claim 14

The circuit according to claim 11 wherein said fifth means comprises a third transistor having a collector coupled to said first voltage, a base coupled to said collector of said first transistor, and an emitter coupled to said first output terminal and said sixth means.

Claim 15

The circuit according to claim 12 wherein said seventh means comprises a fourth transistor having a drain coupled to said emitter of said third transistor, a gate coupled to receive a first enable signal, and a source coupled to said base of said first transistor.

Claim 16

The circuit according to claim 12 wherein said sixth means comprises a fourth transistor having a collector coupled to said first voltage, a base coupled to said collector of said second transistor, and an emitter coupled to said second output terminal and said fifth means.

Claim 17

The circuit according to claim 14 wherein said eighth means comprises a fifth transistor having a source coupled to said emitter of said fourth transistor, a gate coupled to receive a second enable signal, and a drain coupled to said base of said second transistor.

Claim 18

The circuit according to claim 15 wherein said seventh means comprises a sixth transistor having a source coupled to said emitter of said third transistor, a gate coupled to receive a first enable signal, and a drain coupled to said base of said first transistor.