Semiconductor memory

Claim 2

A semiconductor memory comprising: a memory array having a plurality of memory cells; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address data designating memory cells from said memory array in response to the timing signals of said first means; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in memory cells designated by said address counter to said external terminal.

Claim 3

A semiconductor memory according to claim 1, wherein each of said memory cells comprises a dynamic type memory cell.

Claim 4

A semiconductor memory according to claim 2, further comprising: an address buffer circuit providing internal address signals for said memory array in response to external address signals; a multiplexor coupled between said memory array and said address buffer and between said memory array and said address counter; and control means including means for controlling said multiplexor to select either internal address signals generated by said address buffer circuit or address data generated by said address counter to apply to said memory array.

Claim 5

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals designating a memory cell row from said memory array in response to the timing signal of said first means, so that said memory cell rows are sequentially designated by said address counter in accordance with the timing signal of said first means; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in the memory cell row designated by said address counter to said external terminal.

Claim 6

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals designating a memory cell row from said memory array in response to the timing signal of said first means, so that said memory cell rows are sequentially designated by said address counter in accordance with the timing signal of said first means; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in the memory cell row designated by said address counter to said external terminal.

Claim 7

A semiconductor memory according to claim 4, wherein said second means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in memory cells designated by said address counter to said converting means in parallel, and wherein said control means further includes means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal.

Claim 8

A semiconductor memory according to claim 5, wherein said converting means includes a shift register.

Claim 9

A semiconductor memory according to claim 6, wherein each of said memory cells comprises a dynamic type memory cell.

Claim 10

A semiconductor memory according to claim 7, further comprising an address decoder coupled between said memory array and said address counter.

Claim 11

A semiconductor memory according to claim 8, further comprising a control circuit, wherein said second means comprises a converting means which is coupled to said external terminal and which converts parallel data into serial data, and a transmitting means which is coupled between said memory array and said converting means and which transmits data stored in the memory cell row designated by said address counter to said converting means in parallel, and wherein said control circuit includes means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal.

Claim 12

A semiconductor memory according to claim 9, wherein said first means includes means for controlling said address counter so that said address counter designates a different memory cell row when said converting means transmits all of the data stored in a previously designated memory cell row to said external terminal.

Claim 13

A semiconductor memory according to claim 10, wherein said converting means includes a shift register.

Claim 14

A semiconductor memory according to claim 10, wherein said first means comprises a timer circuit for generating said timing signals.

Claim 15

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals in response to the timing signals of said first means; an address buffer circuit providing internal address signals in response to external address signals; a multiplexor coupled between said memory array and said address buffer and between said memory array and said address counter; control means including means for controlling said multiplexor to select either the internal address signals generated by said address buffer circuit or the address signals generated by said address counter; an address decoder coupled between said memory array and said multiplexor, said address decoder including means for selecting a memory cell row from said memory array in response to the address signals selected by said multiplexor; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in a memory cell row, which memory cell row is selected by the address signals which said address counter generates, to said external terminal in series.

Claim 16

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals in response to the timing signals of said first means; an address buffer circuit providing internal address signals in response to external address signals; a multiplexor coupled between said memory array and said address buffer and between said memory array and said address counter; control means including means for controlling said multiplexor to select either the internal address signals generated by said address buffer circuit or the address signals generated by said address counter; an address decoder coupled between said memory array and said multiplexor, said address decoder including means for selecting a memory cell row from said memory array in response to the address signals selected by said multiplexor; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in a memory cell row, which memory cell row is selected by the address signals which said address counter generates, to said external terminal in series.

Claim 17

A semiconductor memory according to claim 13, wherein each of said memory cells comprises a dynamic type memory cell.

Claim 18

A semiconductor memory according to claim 14, wherein said second means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in the memory cell row selected by the address signals of said address counter to said converting means in parallel, and wherein said control means further includes means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal.

Claim 19

A semiconductor memory according to claim 15, wherein said first means includes means for controlling said address counter so that said address counter designates a different memory cell row when said converting means transmits all of the data stored in a previously designated memory cell row to said external terminal.

Claim 20

A semiconductor memory according to claim 16, wherein said converting means includes a shift register.

Claim 21

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals in response to the timing signals of said first means without the need of receiving external address signals; an address buffer circuit providing internal address signals in response to external address signals; a multiplexor coupled between said memory array and said address buffer and between said memory array and said address counter; control means including means for controlling said multiplexor to select either the internal address signals generated by said address buffer circuit or the address signals generated by said address counter; an address decoder coupled between said memory array and said multiplexor, said address decoder including means for selecting a memory cell row from said memory array in response to the address signals selected by said multiplexor; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in a memory cell row, which memory cell row is selected by the address signals which said address counter generates, to said external terminal in series.

Claim 22

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; first means for generating timing signals in a time series manner without the need of receiving external clock signals; an address counter coupled to said first means, said address counter including means for generating address signals in response to the timing signals of said first means without the need of receiving external address signals; an address buffer circuit providing internal address signals in response to external address signals; a multiplexor coupled between said memory array and said address buffer and between said memory array and said address counter; control means including means for controlling said multiplexor to select either the internal address signals generated by said address buffer circuit or the address signals generated by said address counter; an address decoder coupled between said memory array and said multiplexor, said address decoder including means for selecting a memory cell row from said memory array in response to the address signals selected by said multiplexor; and second means coupled to said memory array and to an external terminal, said second means including means for serially transmitting data stored in a memory cell row, which memory cell row is selected by the address signals which said address counter generates, to said external terminal in series.

Claim 23

A semiconductor memory according to claim 18, wherein each of said memory cells comprises a dynamic type memory cell.

Claim 24

A semiconductor memory according to claim 19, wherein said second means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in the memory cell row selected by the address signals of said address counter to said converting means in parallel, and wherein said control means further includes means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal.

Claim 25

A semiconductor memory according to claim 20, wherein said first means includes means for controlling said address counter so that said address counter designates a different memory cell row when said converting means transmits all of the data stored in a previously designated memory cell row to said external terminal.

Claim 26

A semiconductor member according to claim 21, wherein said converting means includes a shift register.

Claim 27

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; address counter means including means for generating address signals designating a memory cell row from said memory array; address decoder means coupled between said memory array and said address counter means, said address decoder means including means for selecting the memory cell row from said memory array in accordance with the address signals generated by said address counter means; and data transmitting means coupled to said memory array and to an external terminal, said data transmitting means including means for serially transmitting data stored in the memory cell row selected by said address decoder means to said external terminal.

Claim 28

A semiconductor memory comprising: a memory array including a plurality of memory cells arranged in rows and columns; address counter means including means for generating address signals designating a memory cell row from said memory array; address decoder means coupled between said memory array and said address counter means, said address decoder means including means for selecting the memory cell row from said memory array in accordance with the address signals generated by said address counter means; and data transmitting means coupled to said memory array and to an external terminal, said data transmitting means including means for serially transmitting data stored in the memory cell row selected by said address decoder means to said external terminal.

Claim 29

A semiconductor memory according to claim 23, wherein each of said memory cells includes a dynamic type memory cell.

Claim 30

A semiconductor memory according to claim 24, further comprising a control circuit, wherein said data transmitting means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in the memory cell row selected by said address decoder means to said converting means in parallel, and wherein said control circuit includes means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal.

Claim 31

A semiconductor memory comprising: a memory array having a plurality of memory cells; first means coupled to said memory array, and for selecting memory cells from said memory array; an external terminal; second means coupled between said memory array and said external terminal, said second means including means for serially transmitting data stored in memory cells selected by said first means to said external terminal in accordance with clock signals; and clock signal generating means for generating said clock signals.

Claim 32

A semiconductor memory comprising: a memory array having a plurality of memory cells; first means coupled to said memory array, and for selecting memory cells from said memory array; an external terminal; second means coupled between said memory array and said external terminal, said second means including means for serially transmitting data stored in memory cells selected by said first means to said external terminal in accordance with clock signals; and clock signal generating means for generating said clock signals.

Claim 33

A semiconductor memory according to claim 26, further comprising a control circuit coupled to said clock signal generating means and to an external terminal for receiving a control signal, wherein said control circuit controls the operation of said clock signal generating means in response to the control signal.

Claim 34

A semiconductor memory according to claim 27, wherein each of said memory cells includes a dynamic type memory cell.

Claim 35

A semiconductor memory comprising: a memory array having a plurality of memory cells; first means coupled to said memory array, and for selecting memory cells from said memory array; an external terminal; second means coupled between said memory array and said external terminal, wherein said second means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in the memory cell row selected by the address signals of said address counter to said converting means in parallel; and control means including means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal, and wherein said second means includes detecting means for detecting a time when said converting means provides all of the data to said external terminal.

Claim 36

A semiconductor memory comprising: a memory array having a plurality of memory cells; first means coupled to said memory array, and for selecting memory cells from said memory array; an external terminal; second means coupled between said memory array and said external terminal, wherein said second means comprises converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in the memory cell row selected by the address signals of said address counter to said converting means in parallel; and control means including means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal, and wherein said second means includes detecting means for detecting a time when said converting means provides all of the data to said external terminal.

Claim 37

A semiconductor memory according to claim 29, wherein said first means includes means responsive to the output signal of said detecting means, for detecting different memory cells from previously selected memory cells.

Claim 38

A semiconductor memory according to claim 30, wherein each of said memory cells includes a dynamic type memory cell.

Claim 39

A semiconductor memory comprising: a memory array including a plurality of dynamic memory cells arranged in rows and columns; an external terminal; first means coupled between said memory array and said external terminal, wherein said first means includes converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in a memory cell row selected from said memory array to said converting means in parallel; control means including means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal; and second means coupled to said memory array, and for selecting a memory cell row during the time that said converting means serially provides previous data to said external terminal, so that the refresh operation of memory cells is executed during said time.

Claim 40

A semiconductor memory comprising: a memory array including a plurality of dynamic memory cells arranged in rows and columns; an external terminal; first means coupled between said memory array and said external terminal, wherein said first means includes converting means coupled to said external terminal and which converts parallel data into serial data, and transmitting means coupled between said memory array and said converting means and which transmits data stored in a memory cell row selected from said memory array to said converting means in parallel; control means including means for controlling said converting means so that said converting means serially provides data applied to said converting means by said transmitting means to said external terminal; and second means coupled to said memory array, and for selecting a memory cell row during the time that said converting means serially provides previous data to said external terminal, so that the refresh operation of memory cells is executed during said time.

Claim 41

A semiconductor memory according to claim 32, wherein said second means includes an address counter for generating address signals, and an address decoder circuit coupled between said memory array and said address counter and for selecting a memory cell row from said memory array.

Claim 42

A semiconductor memory according to claim 33, wherein each of said dynamic memory cells includes a switching MOSFET, and a capacitor means coupled to said switching MOSFET and for storing data.

Claim 43

A semiconductor memory according to claim 1, wherein said address counter generates said address data without the need of receiving external address signals.

Claim 44

A semiconductor memory according to claim 4, wherein said address counter generates said address data without the need of receiving external address signals.